From a304695ffd74b1e26771c97b9da10a4a8247278d Mon Sep 17 00:00:00 2001
From: jackkoenig <jack.koenig3@eecs.berkeley.edu>
Date: Wed, 14 Sep 2016 17:33:39 -0700
Subject: [PATCH] Add firrtl and verilog Makefile targets to vsim

---
 vsim/Makefrag-verilog | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/vsim/Makefrag-verilog b/vsim/Makefrag-verilog
index 9cab4cc9..d8a3f062 100644
--- a/vsim/Makefrag-verilog
+++ b/vsim/Makefrag-verilog
@@ -5,6 +5,11 @@
 # files.
 .SECONDARY: $(generated_dir)/$(MODEL).$(CONFIG).fir
 
+firrtl: $(generated_dir)/$(MODEL).$(CONFIG).fir
+verilog: $(generated_dir)/$(MODEL).$(CONFIG).v
+
+.PHONY: firrtl verilog
+
 $(generated_dir)/%.$(CONFIG).fir $(generated_dir)/%.$(CONFIG).d $(generated_dir)/%.prm: $(chisel_srcs) $(bootrom_img)
 	mkdir -p $(dir $@)
 	cd $(base_dir) && $(SBT) "run $(generated_dir) $(PROJECT) $(notdir $*) $(CFG_PROJECT) $(CONFIG)"