riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Add firrtl and verilog Makefile targets to vsim

Browse Source
This commit is contained in:
jackkoenig 2016-09-14 17:33:39 -07:00 committed by Howard Mao
parent cde104b3fa
commit a304695ffd
1 changed files with 5 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
vsim/Makefrag-verilog
View File

@ -5,6 +5,11 @@
# files. # files.
.SECONDARY: $(generated_dir)/$(MODEL).$(CONFIG).fir .SECONDARY: $(generated_dir)/$(MODEL).$(CONFIG).fir
firrtl: $(generated_dir)/$(MODEL).$(CONFIG).fir
verilog: $(generated_dir)/$(MODEL).$(CONFIG).v
.PHONY: firrtl verilog
$(generated_dir)/%.$(CONFIG).fir $(generated_dir)/%.$(CONFIG).d $(generated_dir)/%.prm: $(chisel_srcs) $(bootrom_img) $(generated_dir)/%.$(CONFIG).fir $(generated_dir)/%.$(CONFIG).d $(generated_dir)/%.prm: $(chisel_srcs) $(bootrom_img)
mkdir -p $(dir $@) mkdir -p $(dir $@)
cd $(base_dir) && $(SBT) "run $(generated_dir) $(PROJECT) $(notdir $*) $(CFG_PROJECT) $(CONFIG)" cd $(base_dir) && $(SBT) "run $(generated_dir) $(PROJECT) $(notdir $*) $(CFG_PROJECT) $(CONFIG)"