rocketchip: rename some periphery ports
This commit is contained in:
Henry Cook
parent
6c3011d513
commit
a281ad8ad2
2
chisel3
2
chisel3
@ -1 +1 @@
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Subproject commit 50db343d5192cd39fa5786e217517c2f139cda64
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Subproject commit 3ef63639284b2b56f415e1540c58d85d88c360db
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2
firrtl
2
firrtl
@ -1 +1 @@
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Subproject commit b69e787c0a698b7fb703ccd8d24003f83207e296
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Subproject commit 568f25b221884eeb0db362c902c933f734c7e47e
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@ -12,6 +12,7 @@ import uncore.devices._
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import util._
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import rocket._
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/** BareTop is the root class for creating a top-level RTL module */
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abstract class BareTop(implicit p: Parameters) extends LazyModule {
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ElaborationArtefacts.add("graphml", graphML)
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}
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@ -26,17 +27,20 @@ abstract class BareTopModule[+L <: BareTop, +B <: BareTopBundle[L]](_outer: L, _
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val io = _io ()
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}
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/** Base Top with no Periphery */
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trait TopNetwork extends HasPeripheryParameters {
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val module: TopNetworkModule
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/** HasTopLevelNetworks provides buses that will serve as attachment points,
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* for use in sub-traits that connect individual agents or external ports.
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*/
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trait HasTopLevelNetworks extends HasPeripheryParameters {
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val module: HasTopLevelNetworksModule
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// Add a SoC and peripheral bus
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val socBus = LazyModule(new TLXbar)
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val peripheryBus = LazyModule(new TLXbar)
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val intBus = LazyModule(new IntXbar)
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val l2 = LazyModule(new TLBuffer)
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val mem = Seq.fill(p(coreplex.BankedL2Config).nMemoryChannels) { LazyModule(new TLXbar) }
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val socBus = LazyModule(new TLXbar) // Wide or unordered-access slave devices (TL-UH)
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val peripheryBus = LazyModule(new TLXbar) // Narrow and ordered-access slave devices (TL-UL)
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val intBus = LazyModule(new IntXbar) // Interrupts
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val l2FrontendBus = LazyModule(new TLBuffer) // Master devices talking to the frontside of the L2
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val mem = Seq.fill(nMemoryChannels) { LazyModule(new TLXbar) } // Ports out to DRAM
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// The peripheryBus hangs off of socBus;
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// here we convert TL-UH -> TL-UL
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peripheryBus.node :=
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TLBuffer()(
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TLWidthWidget(socBusConfig.beatBytes)(
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@ -44,23 +48,23 @@ trait TopNetwork extends HasPeripheryParameters {
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socBus.node)))
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}
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trait TopNetworkBundle extends HasPeripheryParameters {
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val outer: TopNetwork
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trait HasTopLevelNetworksBundle extends HasPeripheryParameters {
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val outer: HasTopLevelNetworks
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}
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trait TopNetworkModule extends HasPeripheryParameters {
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val io: TopNetworkBundle
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val outer: TopNetwork
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trait HasTopLevelNetworksModule extends HasPeripheryParameters {
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val outer: HasTopLevelNetworks
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val io: HasTopLevelNetworksBundle
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}
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/** Base Top with no Periphery */
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/** Base Top class with no peripheral devices or ports added */
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class BaseTop(implicit p: Parameters) extends BareTop
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with TopNetwork {
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with HasTopLevelNetworks {
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override lazy val module = new BaseTopModule(this, () => new BaseTopBundle(this))
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}
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class BaseTopBundle[+L <: BaseTop](_outer: L) extends BareTopBundle(_outer)
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with TopNetworkBundle
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with HasTopLevelNetworksBundle
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class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle[L]](_outer: L, _io: () => B) extends BareTopModule(_outer, _io)
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with TopNetworkModule
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with HasTopLevelNetworksModule
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@ -37,16 +37,17 @@ case object ZeroConfig extends Field[ZeroConfig]
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/** Utility trait for quick access to some relevant parameters */
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trait HasPeripheryParameters {
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implicit val p: Parameters
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lazy val peripheryBusConfig = p(PeripheryBusConfig)
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lazy val socBusConfig = p(SOCBusConfig)
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lazy val cacheBlockBytes = p(CacheBlockBytes)
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lazy val peripheryBusArithmetic = p(PeripheryBusArithmetic)
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def peripheryBusConfig = p(PeripheryBusConfig)
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def socBusConfig = p(SOCBusConfig)
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def cacheBlockBytes = p(CacheBlockBytes)
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def peripheryBusArithmetic = p(PeripheryBusArithmetic)
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def nMemoryChannels = p(coreplex.BankedL2Config).nMemoryChannels
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}
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/////
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trait PeripheryExtInterrupts {
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this: TopNetwork =>
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this: HasTopLevelNetworks =>
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val nExtInterrupts = p(NExtTopInterrupts)
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val extInterrupts = IntInternalInputNode(nExtInterrupts)
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@ -57,14 +58,14 @@ trait PeripheryExtInterrupts {
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}
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trait PeripheryExtInterruptsBundle {
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this: TopNetworkBundle {
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this: HasTopLevelNetworksBundle {
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val outer: PeripheryExtInterrupts
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} =>
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val interrupts = UInt(INPUT, width = outer.nExtInterrupts)
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}
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trait PeripheryExtInterruptsModule {
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this: TopNetworkModule {
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this: HasTopLevelNetworksModule {
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val outer: PeripheryExtInterrupts
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val io: PeripheryExtInterruptsBundle
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} =>
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@ -74,7 +75,7 @@ trait PeripheryExtInterruptsModule {
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/////
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trait PeripheryMasterAXI4Mem {
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this: TopNetwork =>
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this: HasTopLevelNetworks =>
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val module: PeripheryMasterAXI4MemModule
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private val config = p(ExtMem)
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@ -107,14 +108,14 @@ trait PeripheryMasterAXI4Mem {
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}
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trait PeripheryMasterAXI4MemBundle {
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this: TopNetworkBundle {
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this: HasTopLevelNetworksBundle {
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val outer: PeripheryMasterAXI4Mem
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} =>
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val mem_axi4 = outer.mem_axi4.bundleOut
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}
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trait PeripheryMasterAXI4MemModule {
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this: TopNetworkModule {
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this: HasTopLevelNetworksModule {
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val outer: PeripheryMasterAXI4Mem
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val io: PeripheryMasterAXI4MemBundle
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} =>
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@ -123,7 +124,7 @@ trait PeripheryMasterAXI4MemModule {
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/////
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trait PeripheryZero {
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this: TopNetwork =>
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this: HasTopLevelNetworks =>
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val module: PeripheryZeroModule
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private val config = p(ZeroConfig)
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@ -138,13 +139,13 @@ trait PeripheryZero {
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}
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trait PeripheryZeroBundle {
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this: TopNetworkBundle {
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this: HasTopLevelNetworksBundle {
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val outer: PeripheryZero
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} =>
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}
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trait PeripheryZeroModule {
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this: TopNetworkModule {
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this: HasTopLevelNetworksModule {
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val outer: PeripheryZero
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val io: PeripheryZeroBundle
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} =>
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@ -154,7 +155,7 @@ trait PeripheryZeroModule {
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// PeripheryMasterAXI4MMIO is an example, make your own cake pattern like this one.
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trait PeripheryMasterAXI4MMIO {
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this: TopNetwork =>
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this: HasTopLevelNetworks =>
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private val config = p(ExtBus)
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val mmio_axi4 = AXI4BlindOutputNode(Seq(AXI4SlavePortParameters(
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@ -175,14 +176,14 @@ trait PeripheryMasterAXI4MMIO {
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}
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trait PeripheryMasterAXI4MMIOBundle {
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this: TopNetworkBundle {
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this: HasTopLevelNetworksBundle {
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val outer: PeripheryMasterAXI4MMIO
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} =>
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val mmio_axi4 = outer.mmio_axi4.bundleOut
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}
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trait PeripheryMasterAXI4MMIOModule {
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this: TopNetworkModule {
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this: HasTopLevelNetworksModule {
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val outer: PeripheryMasterAXI4MMIO
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val io: PeripheryMasterAXI4MMIOBundle
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} =>
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@ -192,26 +193,26 @@ trait PeripheryMasterAXI4MMIOModule {
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/////
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// PeripherySlaveAXI4 is an example, make your own cake pattern like this one.
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trait PeripherySlaveAXI4 extends TopNetwork {
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trait PeripherySlaveAXI4 extends HasTopLevelNetworks {
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private val config = p(ExtIn)
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val l2_axi4 = AXI4BlindInputNode(Seq(AXI4MasterPortParameters(
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val l2FrontendAXI4Node = AXI4BlindInputNode(Seq(AXI4MasterPortParameters(
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masters = Seq(AXI4MasterParameters(
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id = IdRange(0, 1 << config.idBits))))))
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l2.node :=
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l2FrontendBus.node :=
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TLSourceShrinker(1 << config.sourceBits)(
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TLWidthWidget(config.beatBytes)(
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AXI4ToTL()(
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AXI4Fragmenter()(
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l2_axi4))))
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l2FrontendAXI4Node))))
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}
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trait PeripherySlaveAXI4Bundle extends TopNetworkBundle {
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trait PeripherySlaveAXI4Bundle extends HasTopLevelNetworksBundle {
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val outer: PeripherySlaveAXI4
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val l2_axi4 = outer.l2_axi4.bundleIn
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val l2_frontend_bus_axi4 = outer.l2FrontendAXI4Node.bundleIn
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}
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trait PeripherySlaveAXI4Module extends TopNetworkModule {
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trait PeripherySlaveAXI4Module extends HasTopLevelNetworksModule {
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val outer: PeripherySlaveAXI4
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val io: PeripherySlaveAXI4Bundle
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// nothing to do
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@ -221,7 +222,7 @@ trait PeripherySlaveAXI4Module extends TopNetworkModule {
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// Add an external TL-UL slave
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trait PeripheryMasterTLMMIO {
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this: TopNetwork =>
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this: HasTopLevelNetworks =>
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private val config = p(ExtBus)
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val mmio_tl = TLBlindOutputNode(Seq(TLManagerPortParameters(
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@ -241,14 +242,14 @@ trait PeripheryMasterTLMMIO {
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}
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trait PeripheryMasterTLMMIOBundle {
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this: TopNetworkBundle {
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this: HasTopLevelNetworksBundle {
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val outer: PeripheryMasterTLMMIO
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} =>
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val mmio_tl = outer.mmio_tl.bundleOut
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}
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trait PeripheryMasterTLMMIOModule {
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this: TopNetworkModule {
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this: HasTopLevelNetworksModule {
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val outer: PeripheryMasterTLMMIO
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val io: PeripheryMasterTLMMIOBundle
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} =>
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@ -258,24 +259,24 @@ trait PeripheryMasterTLMMIOModule {
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/////
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// NOTE: this port is NOT allowed to issue Acquires
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trait PeripherySlaveTL extends TopNetwork {
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trait PeripherySlaveTL extends HasTopLevelNetworks {
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private val config = p(ExtIn)
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val l2_tl = TLBlindInputNode(Seq(TLClientPortParameters(
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val l2FrontendTLNode = TLBlindInputNode(Seq(TLClientPortParameters(
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clients = Seq(TLClientParameters(
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sourceId = IdRange(0, 1 << config.idBits))))))
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l2.node :=
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l2FrontendBus.node :=
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TLSourceShrinker(1 << config.sourceBits)(
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TLWidthWidget(config.beatBytes)(
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l2_tl))
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l2FrontendTLNode))
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}
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trait PeripherySlaveTLBundle extends TopNetworkBundle {
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trait PeripherySlaveTLBundle extends HasTopLevelNetworksBundle {
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val outer: PeripherySlaveTL
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val l2_tl = outer.l2_tl.bundleIn
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val l2_frontend_bus_tl = outer.l2FrontendTLNode.bundleIn
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}
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trait PeripherySlaveTLModule extends TopNetworkModule {
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trait PeripherySlaveTLModule extends HasTopLevelNetworksModule {
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val outer: PeripherySlaveTL
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val io: PeripherySlaveTLBundle
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// nothing to do
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@ -284,7 +285,7 @@ trait PeripherySlaveTLModule extends TopNetworkModule {
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/////
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trait PeripheryBootROM {
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this: TopNetwork =>
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this: HasTopLevelNetworks =>
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val coreplex: CoreplexRISCVPlatform
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private val bootrom_address = 0x1000
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@ -295,13 +296,13 @@ trait PeripheryBootROM {
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}
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trait PeripheryBootROMBundle {
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this: TopNetworkBundle {
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this: HasTopLevelNetworksBundle {
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val outer: PeripheryBootROM
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} =>
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}
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trait PeripheryBootROMModule {
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this: TopNetworkModule {
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this: HasTopLevelNetworksModule {
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val outer: PeripheryBootROM
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val io: PeripheryBootROMBundle
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} =>
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@ -310,20 +311,20 @@ trait PeripheryBootROMModule {
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/////
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trait PeripheryTestRAM {
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this: TopNetwork =>
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this: HasTopLevelNetworks =>
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val testram = LazyModule(new TLRAM(AddressSet(0x52000000, 0xfff), true, peripheryBusConfig.beatBytes))
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testram.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
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}
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trait PeripheryTestRAMBundle {
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this: TopNetworkBundle {
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this: HasTopLevelNetworksBundle {
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val outer: PeripheryTestRAM
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} =>
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}
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trait PeripheryTestRAMModule {
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this: TopNetworkModule {
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this: HasTopLevelNetworksModule {
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val outer: PeripheryTestRAM
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val io: PeripheryTestRAMBundle
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} =>
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@ -332,19 +333,19 @@ trait PeripheryTestRAMModule {
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/////
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trait PeripheryTestBusMaster {
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this: TopNetwork =>
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this: HasTopLevelNetworks =>
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val fuzzer = LazyModule(new TLFuzzer(5000))
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peripheryBus.node := fuzzer.node
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}
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trait PeripheryTestBusMasterBundle {
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this: TopNetworkBundle {
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this: HasTopLevelNetworksBundle {
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val outer: PeripheryTestBusMaster
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} =>
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}
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trait PeripheryTestBusMasterModule {
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this: TopNetworkModule {
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this: HasTopLevelNetworksModule {
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val outer: PeripheryTestBusMaster
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val io: PeripheryTestBusMasterBundle
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} =>
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@ -13,18 +13,18 @@ import coreplex._
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/// Core with JTAG for debug only
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trait PeripheryJTAG extends TopNetwork {
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trait PeripheryJTAG extends HasTopLevelNetworks {
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val module: PeripheryJTAGModule
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val coreplex: CoreplexRISCVPlatform
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}
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trait PeripheryJTAGBundle extends TopNetworkBundle {
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trait PeripheryJTAGBundle extends HasTopLevelNetworksBundle {
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val outer: PeripheryJTAG
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val jtag = new JTAGIO(true).flip
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}
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trait PeripheryJTAGModule extends TopNetworkModule {
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trait PeripheryJTAGModule extends HasTopLevelNetworksModule {
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val outer: PeripheryJTAG
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val io: PeripheryJTAGBundle
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@ -38,18 +38,18 @@ trait PeripheryJTAGModule extends TopNetworkModule {
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/// Core with DTM for debug only
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trait PeripheryDTM extends TopNetwork {
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trait PeripheryDTM extends HasTopLevelNetworks {
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val module: PeripheryDTMModule
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val coreplex: CoreplexRISCVPlatform
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}
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trait PeripheryDTMBundle extends TopNetworkBundle {
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trait PeripheryDTMBundle extends HasTopLevelNetworksBundle {
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val outer: PeripheryDTM
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val debug = new DebugBusIO().flip
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}
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trait PeripheryDTMModule extends TopNetworkModule {
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trait PeripheryDTMModule extends HasTopLevelNetworksModule {
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val outer: PeripheryDTM
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val io: PeripheryDTMBundle
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@ -58,19 +58,19 @@ trait PeripheryDTMModule extends TopNetworkModule {
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/// Core with DTM or JTAG based on a parameter
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trait PeripheryDebug extends TopNetwork {
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trait PeripheryDebug extends HasTopLevelNetworks {
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val module: PeripheryDebugModule
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val coreplex: CoreplexRISCVPlatform
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}
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trait PeripheryDebugBundle extends TopNetworkBundle {
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trait PeripheryDebugBundle extends HasTopLevelNetworksBundle {
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val outer: PeripheryDebug
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val debug = (!p(IncludeJtagDTM)).option(new DebugBusIO().flip)
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val jtag = (p(IncludeJtagDTM)).option(new JTAGIO(true).flip)
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}
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trait PeripheryDebugModule extends TopNetworkModule {
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trait PeripheryDebugModule extends HasTopLevelNetworksModule {
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val outer: PeripheryDebug
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val io: PeripheryDebugBundle
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@ -86,16 +86,16 @@ trait PeripheryDebugModule extends TopNetworkModule {
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/// Real-time clock is based on RTCPeriod relative to Top clock
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trait PeripheryCounter extends TopNetwork {
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trait PeripheryCounter extends HasTopLevelNetworks {
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val module: PeripheryCounterModule
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val coreplex: CoreplexRISCVPlatform
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}
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trait PeripheryCounterBundle extends TopNetworkBundle {
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trait PeripheryCounterBundle extends HasTopLevelNetworksBundle {
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val outer: PeripheryCounter
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}
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trait PeripheryCounterModule extends TopNetworkModule {
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trait PeripheryCounterModule extends HasTopLevelNetworksModule {
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val outer: PeripheryCounter
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val io: PeripheryCounterBundle
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@ -111,16 +111,16 @@ trait PeripheryCounterModule extends TopNetworkModule {
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/// Coreplex will power-on running at 0x1000 (BootROM)
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trait HardwiredResetVector extends TopNetwork {
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trait HardwiredResetVector extends HasTopLevelNetworks {
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val module: HardwiredResetVectorModule
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val coreplex: CoreplexRISCVPlatform
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}
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trait HardwiredResetVectorBundle extends TopNetworkBundle {
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trait HardwiredResetVectorBundle extends HasTopLevelNetworksBundle {
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val outer: HardwiredResetVector
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}
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trait HardwiredResetVectorModule extends TopNetworkModule {
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trait HardwiredResetVectorModule extends HasTopLevelNetworksModule {
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val outer: HardwiredResetVector
|
||||
val io: HardwiredResetVectorBundle
|
||||
|
||||
|
||||
@ -10,12 +10,12 @@ import uncore.devices._
|
||||
import util._
|
||||
import coreplex._
|
||||
|
||||
trait RocketPlexMaster extends TopNetwork {
|
||||
trait RocketPlexMaster extends HasTopLevelNetworks {
|
||||
val module: RocketPlexMasterModule
|
||||
|
||||
val coreplex = LazyModule(new DefaultCoreplex)
|
||||
|
||||
coreplex.l2in :=* l2.node
|
||||
coreplex.l2in :=* l2FrontendBus.node
|
||||
socBus.node := coreplex.mmio
|
||||
coreplex.mmioInt := intBus.intnode
|
||||
|
||||
@ -23,11 +23,11 @@ trait RocketPlexMaster extends TopNetwork {
|
||||
(mem zip coreplex.mem) foreach { case (xbar, channel) => xbar.node :=* channel }
|
||||
}
|
||||
|
||||
trait RocketPlexMasterBundle extends TopNetworkBundle {
|
||||
trait RocketPlexMasterBundle extends HasTopLevelNetworksBundle {
|
||||
val outer: RocketPlexMaster
|
||||
}
|
||||
|
||||
trait RocketPlexMasterModule extends TopNetworkModule {
|
||||
trait RocketPlexMasterModule extends HasTopLevelNetworksModule {
|
||||
val outer: RocketPlexMaster
|
||||
val io: RocketPlexMasterBundle
|
||||
val clock: Clock
|
||||
|
||||
@ -29,7 +29,7 @@ class TestHarness()(implicit p: Parameters) extends Module {
|
||||
val mmio_sim = Module(LazyModule(new SimAXIMem(1, 4096)).module)
|
||||
mmio_sim.io.axi4 <> dut.io.mmio_axi4
|
||||
|
||||
val l2_axi4 = dut.io.l2_axi4(0)
|
||||
val l2_axi4 = dut.io.l2_frontend_bus_axi4(0)
|
||||
l2_axi4.ar.valid := Bool(false)
|
||||
l2_axi4.aw.valid := Bool(false)
|
||||
l2_axi4.w .valid := Bool(false)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user