diff --git a/chisel3 b/chisel3 index 50db343d..3ef63639 160000 --- a/chisel3 +++ b/chisel3 @@ -1 +1 @@ -Subproject commit 50db343d5192cd39fa5786e217517c2f139cda64 +Subproject commit 3ef63639284b2b56f415e1540c58d85d88c360db diff --git a/firrtl b/firrtl index b69e787c..568f25b2 160000 --- a/firrtl +++ b/firrtl @@ -1 +1 @@ -Subproject commit b69e787c0a698b7fb703ccd8d24003f83207e296 +Subproject commit 568f25b221884eeb0db362c902c933f734c7e47e diff --git a/src/main/scala/rocketchip/BaseTop.scala b/src/main/scala/rocketchip/BaseTop.scala index b5a8c582..7e2638d3 100644 --- a/src/main/scala/rocketchip/BaseTop.scala +++ b/src/main/scala/rocketchip/BaseTop.scala @@ -12,6 +12,7 @@ import uncore.devices._ import util._ import rocket._ +/** BareTop is the root class for creating a top-level RTL module */ abstract class BareTop(implicit p: Parameters) extends LazyModule { ElaborationArtefacts.add("graphml", graphML) } @@ -26,17 +27,20 @@ abstract class BareTopModule[+L <: BareTop, +B <: BareTopBundle[L]](_outer: L, _ val io = _io () } -/** Base Top with no Periphery */ -trait TopNetwork extends HasPeripheryParameters { - val module: TopNetworkModule +/** HasTopLevelNetworks provides buses that will serve as attachment points, + * for use in sub-traits that connect individual agents or external ports. + */ +trait HasTopLevelNetworks extends HasPeripheryParameters { + val module: HasTopLevelNetworksModule - // Add a SoC and peripheral bus - val socBus = LazyModule(new TLXbar) - val peripheryBus = LazyModule(new TLXbar) - val intBus = LazyModule(new IntXbar) - val l2 = LazyModule(new TLBuffer) - val mem = Seq.fill(p(coreplex.BankedL2Config).nMemoryChannels) { LazyModule(new TLXbar) } + val socBus = LazyModule(new TLXbar) // Wide or unordered-access slave devices (TL-UH) + val peripheryBus = LazyModule(new TLXbar) // Narrow and ordered-access slave devices (TL-UL) + val intBus = LazyModule(new IntXbar) // Interrupts + val l2FrontendBus = LazyModule(new TLBuffer) // Master devices talking to the frontside of the L2 + val mem = Seq.fill(nMemoryChannels) { LazyModule(new TLXbar) } // Ports out to DRAM + // The peripheryBus hangs off of socBus; + // here we convert TL-UH -> TL-UL peripheryBus.node := TLBuffer()( TLWidthWidget(socBusConfig.beatBytes)( @@ -44,23 +48,23 @@ trait TopNetwork extends HasPeripheryParameters { socBus.node))) } -trait TopNetworkBundle extends HasPeripheryParameters { - val outer: TopNetwork +trait HasTopLevelNetworksBundle extends HasPeripheryParameters { + val outer: HasTopLevelNetworks } -trait TopNetworkModule extends HasPeripheryParameters { - val io: TopNetworkBundle - val outer: TopNetwork +trait HasTopLevelNetworksModule extends HasPeripheryParameters { + val outer: HasTopLevelNetworks + val io: HasTopLevelNetworksBundle } -/** Base Top with no Periphery */ +/** Base Top class with no peripheral devices or ports added */ class BaseTop(implicit p: Parameters) extends BareTop - with TopNetwork { + with HasTopLevelNetworks { override lazy val module = new BaseTopModule(this, () => new BaseTopBundle(this)) } class BaseTopBundle[+L <: BaseTop](_outer: L) extends BareTopBundle(_outer) - with TopNetworkBundle + with HasTopLevelNetworksBundle class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle[L]](_outer: L, _io: () => B) extends BareTopModule(_outer, _io) - with TopNetworkModule + with HasTopLevelNetworksModule diff --git a/src/main/scala/rocketchip/Periphery.scala b/src/main/scala/rocketchip/Periphery.scala index b504839f..e495ef33 100644 --- a/src/main/scala/rocketchip/Periphery.scala +++ b/src/main/scala/rocketchip/Periphery.scala @@ -37,16 +37,17 @@ case object ZeroConfig extends Field[ZeroConfig] /** Utility trait for quick access to some relevant parameters */ trait HasPeripheryParameters { implicit val p: Parameters - lazy val peripheryBusConfig = p(PeripheryBusConfig) - lazy val socBusConfig = p(SOCBusConfig) - lazy val cacheBlockBytes = p(CacheBlockBytes) - lazy val peripheryBusArithmetic = p(PeripheryBusArithmetic) + def peripheryBusConfig = p(PeripheryBusConfig) + def socBusConfig = p(SOCBusConfig) + def cacheBlockBytes = p(CacheBlockBytes) + def peripheryBusArithmetic = p(PeripheryBusArithmetic) + def nMemoryChannels = p(coreplex.BankedL2Config).nMemoryChannels } ///// trait PeripheryExtInterrupts { - this: TopNetwork => + this: HasTopLevelNetworks => val nExtInterrupts = p(NExtTopInterrupts) val extInterrupts = IntInternalInputNode(nExtInterrupts) @@ -57,14 +58,14 @@ trait PeripheryExtInterrupts { } trait PeripheryExtInterruptsBundle { - this: TopNetworkBundle { + this: HasTopLevelNetworksBundle { val outer: PeripheryExtInterrupts } => val interrupts = UInt(INPUT, width = outer.nExtInterrupts) } trait PeripheryExtInterruptsModule { - this: TopNetworkModule { + this: HasTopLevelNetworksModule { val outer: PeripheryExtInterrupts val io: PeripheryExtInterruptsBundle } => @@ -74,7 +75,7 @@ trait PeripheryExtInterruptsModule { ///// trait PeripheryMasterAXI4Mem { - this: TopNetwork => + this: HasTopLevelNetworks => val module: PeripheryMasterAXI4MemModule private val config = p(ExtMem) @@ -107,14 +108,14 @@ trait PeripheryMasterAXI4Mem { } trait PeripheryMasterAXI4MemBundle { - this: TopNetworkBundle { + this: HasTopLevelNetworksBundle { val outer: PeripheryMasterAXI4Mem } => val mem_axi4 = outer.mem_axi4.bundleOut } trait PeripheryMasterAXI4MemModule { - this: TopNetworkModule { + this: HasTopLevelNetworksModule { val outer: PeripheryMasterAXI4Mem val io: PeripheryMasterAXI4MemBundle } => @@ -123,7 +124,7 @@ trait PeripheryMasterAXI4MemModule { ///// trait PeripheryZero { - this: TopNetwork => + this: HasTopLevelNetworks => val module: PeripheryZeroModule private val config = p(ZeroConfig) @@ -138,13 +139,13 @@ trait PeripheryZero { } trait PeripheryZeroBundle { - this: TopNetworkBundle { + this: HasTopLevelNetworksBundle { val outer: PeripheryZero } => } trait PeripheryZeroModule { - this: TopNetworkModule { + this: HasTopLevelNetworksModule { val outer: PeripheryZero val io: PeripheryZeroBundle } => @@ -154,7 +155,7 @@ trait PeripheryZeroModule { // PeripheryMasterAXI4MMIO is an example, make your own cake pattern like this one. trait PeripheryMasterAXI4MMIO { - this: TopNetwork => + this: HasTopLevelNetworks => private val config = p(ExtBus) val mmio_axi4 = AXI4BlindOutputNode(Seq(AXI4SlavePortParameters( @@ -175,14 +176,14 @@ trait PeripheryMasterAXI4MMIO { } trait PeripheryMasterAXI4MMIOBundle { - this: TopNetworkBundle { + this: HasTopLevelNetworksBundle { val outer: PeripheryMasterAXI4MMIO } => val mmio_axi4 = outer.mmio_axi4.bundleOut } trait PeripheryMasterAXI4MMIOModule { - this: TopNetworkModule { + this: HasTopLevelNetworksModule { val outer: PeripheryMasterAXI4MMIO val io: PeripheryMasterAXI4MMIOBundle } => @@ -192,26 +193,26 @@ trait PeripheryMasterAXI4MMIOModule { ///// // PeripherySlaveAXI4 is an example, make your own cake pattern like this one. -trait PeripherySlaveAXI4 extends TopNetwork { +trait PeripherySlaveAXI4 extends HasTopLevelNetworks { private val config = p(ExtIn) - val l2_axi4 = AXI4BlindInputNode(Seq(AXI4MasterPortParameters( + val l2FrontendAXI4Node = AXI4BlindInputNode(Seq(AXI4MasterPortParameters( masters = Seq(AXI4MasterParameters( id = IdRange(0, 1 << config.idBits)))))) - l2.node := + l2FrontendBus.node := TLSourceShrinker(1 << config.sourceBits)( TLWidthWidget(config.beatBytes)( AXI4ToTL()( AXI4Fragmenter()( - l2_axi4)))) + l2FrontendAXI4Node)))) } -trait PeripherySlaveAXI4Bundle extends TopNetworkBundle { +trait PeripherySlaveAXI4Bundle extends HasTopLevelNetworksBundle { val outer: PeripherySlaveAXI4 - val l2_axi4 = outer.l2_axi4.bundleIn + val l2_frontend_bus_axi4 = outer.l2FrontendAXI4Node.bundleIn } -trait PeripherySlaveAXI4Module extends TopNetworkModule { +trait PeripherySlaveAXI4Module extends HasTopLevelNetworksModule { val outer: PeripherySlaveAXI4 val io: PeripherySlaveAXI4Bundle // nothing to do @@ -221,7 +222,7 @@ trait PeripherySlaveAXI4Module extends TopNetworkModule { // Add an external TL-UL slave trait PeripheryMasterTLMMIO { - this: TopNetwork => + this: HasTopLevelNetworks => private val config = p(ExtBus) val mmio_tl = TLBlindOutputNode(Seq(TLManagerPortParameters( @@ -241,14 +242,14 @@ trait PeripheryMasterTLMMIO { } trait PeripheryMasterTLMMIOBundle { - this: TopNetworkBundle { + this: HasTopLevelNetworksBundle { val outer: PeripheryMasterTLMMIO } => val mmio_tl = outer.mmio_tl.bundleOut } trait PeripheryMasterTLMMIOModule { - this: TopNetworkModule { + this: HasTopLevelNetworksModule { val outer: PeripheryMasterTLMMIO val io: PeripheryMasterTLMMIOBundle } => @@ -258,24 +259,24 @@ trait PeripheryMasterTLMMIOModule { ///// // NOTE: this port is NOT allowed to issue Acquires -trait PeripherySlaveTL extends TopNetwork { +trait PeripherySlaveTL extends HasTopLevelNetworks { private val config = p(ExtIn) - val l2_tl = TLBlindInputNode(Seq(TLClientPortParameters( + val l2FrontendTLNode = TLBlindInputNode(Seq(TLClientPortParameters( clients = Seq(TLClientParameters( sourceId = IdRange(0, 1 << config.idBits)))))) - l2.node := + l2FrontendBus.node := TLSourceShrinker(1 << config.sourceBits)( TLWidthWidget(config.beatBytes)( - l2_tl)) + l2FrontendTLNode)) } -trait PeripherySlaveTLBundle extends TopNetworkBundle { +trait PeripherySlaveTLBundle extends HasTopLevelNetworksBundle { val outer: PeripherySlaveTL - val l2_tl = outer.l2_tl.bundleIn + val l2_frontend_bus_tl = outer.l2FrontendTLNode.bundleIn } -trait PeripherySlaveTLModule extends TopNetworkModule { +trait PeripherySlaveTLModule extends HasTopLevelNetworksModule { val outer: PeripherySlaveTL val io: PeripherySlaveTLBundle // nothing to do @@ -284,7 +285,7 @@ trait PeripherySlaveTLModule extends TopNetworkModule { ///// trait PeripheryBootROM { - this: TopNetwork => + this: HasTopLevelNetworks => val coreplex: CoreplexRISCVPlatform private val bootrom_address = 0x1000 @@ -295,13 +296,13 @@ trait PeripheryBootROM { } trait PeripheryBootROMBundle { - this: TopNetworkBundle { + this: HasTopLevelNetworksBundle { val outer: PeripheryBootROM } => } trait PeripheryBootROMModule { - this: TopNetworkModule { + this: HasTopLevelNetworksModule { val outer: PeripheryBootROM val io: PeripheryBootROMBundle } => @@ -310,20 +311,20 @@ trait PeripheryBootROMModule { ///// trait PeripheryTestRAM { - this: TopNetwork => + this: HasTopLevelNetworks => val testram = LazyModule(new TLRAM(AddressSet(0x52000000, 0xfff), true, peripheryBusConfig.beatBytes)) testram.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node) } trait PeripheryTestRAMBundle { - this: TopNetworkBundle { + this: HasTopLevelNetworksBundle { val outer: PeripheryTestRAM } => } trait PeripheryTestRAMModule { - this: TopNetworkModule { + this: HasTopLevelNetworksModule { val outer: PeripheryTestRAM val io: PeripheryTestRAMBundle } => @@ -332,19 +333,19 @@ trait PeripheryTestRAMModule { ///// trait PeripheryTestBusMaster { - this: TopNetwork => + this: HasTopLevelNetworks => val fuzzer = LazyModule(new TLFuzzer(5000)) peripheryBus.node := fuzzer.node } trait PeripheryTestBusMasterBundle { - this: TopNetworkBundle { + this: HasTopLevelNetworksBundle { val outer: PeripheryTestBusMaster } => } trait PeripheryTestBusMasterModule { - this: TopNetworkModule { + this: HasTopLevelNetworksModule { val outer: PeripheryTestBusMaster val io: PeripheryTestBusMasterBundle } => diff --git a/src/main/scala/rocketchip/RISCVPlatform.scala b/src/main/scala/rocketchip/RISCVPlatform.scala index 35aae1fc..7bc9779a 100644 --- a/src/main/scala/rocketchip/RISCVPlatform.scala +++ b/src/main/scala/rocketchip/RISCVPlatform.scala @@ -13,18 +13,18 @@ import coreplex._ /// Core with JTAG for debug only -trait PeripheryJTAG extends TopNetwork { +trait PeripheryJTAG extends HasTopLevelNetworks { val module: PeripheryJTAGModule val coreplex: CoreplexRISCVPlatform } -trait PeripheryJTAGBundle extends TopNetworkBundle { +trait PeripheryJTAGBundle extends HasTopLevelNetworksBundle { val outer: PeripheryJTAG val jtag = new JTAGIO(true).flip } -trait PeripheryJTAGModule extends TopNetworkModule { +trait PeripheryJTAGModule extends HasTopLevelNetworksModule { val outer: PeripheryJTAG val io: PeripheryJTAGBundle @@ -38,18 +38,18 @@ trait PeripheryJTAGModule extends TopNetworkModule { /// Core with DTM for debug only -trait PeripheryDTM extends TopNetwork { +trait PeripheryDTM extends HasTopLevelNetworks { val module: PeripheryDTMModule val coreplex: CoreplexRISCVPlatform } -trait PeripheryDTMBundle extends TopNetworkBundle { +trait PeripheryDTMBundle extends HasTopLevelNetworksBundle { val outer: PeripheryDTM val debug = new DebugBusIO().flip } -trait PeripheryDTMModule extends TopNetworkModule { +trait PeripheryDTMModule extends HasTopLevelNetworksModule { val outer: PeripheryDTM val io: PeripheryDTMBundle @@ -58,19 +58,19 @@ trait PeripheryDTMModule extends TopNetworkModule { /// Core with DTM or JTAG based on a parameter -trait PeripheryDebug extends TopNetwork { +trait PeripheryDebug extends HasTopLevelNetworks { val module: PeripheryDebugModule val coreplex: CoreplexRISCVPlatform } -trait PeripheryDebugBundle extends TopNetworkBundle { +trait PeripheryDebugBundle extends HasTopLevelNetworksBundle { val outer: PeripheryDebug val debug = (!p(IncludeJtagDTM)).option(new DebugBusIO().flip) val jtag = (p(IncludeJtagDTM)).option(new JTAGIO(true).flip) } -trait PeripheryDebugModule extends TopNetworkModule { +trait PeripheryDebugModule extends HasTopLevelNetworksModule { val outer: PeripheryDebug val io: PeripheryDebugBundle @@ -86,16 +86,16 @@ trait PeripheryDebugModule extends TopNetworkModule { /// Real-time clock is based on RTCPeriod relative to Top clock -trait PeripheryCounter extends TopNetwork { +trait PeripheryCounter extends HasTopLevelNetworks { val module: PeripheryCounterModule val coreplex: CoreplexRISCVPlatform } -trait PeripheryCounterBundle extends TopNetworkBundle { +trait PeripheryCounterBundle extends HasTopLevelNetworksBundle { val outer: PeripheryCounter } -trait PeripheryCounterModule extends TopNetworkModule { +trait PeripheryCounterModule extends HasTopLevelNetworksModule { val outer: PeripheryCounter val io: PeripheryCounterBundle @@ -111,16 +111,16 @@ trait PeripheryCounterModule extends TopNetworkModule { /// Coreplex will power-on running at 0x1000 (BootROM) -trait HardwiredResetVector extends TopNetwork { +trait HardwiredResetVector extends HasTopLevelNetworks { val module: HardwiredResetVectorModule val coreplex: CoreplexRISCVPlatform } -trait HardwiredResetVectorBundle extends TopNetworkBundle { +trait HardwiredResetVectorBundle extends HasTopLevelNetworksBundle { val outer: HardwiredResetVector } -trait HardwiredResetVectorModule extends TopNetworkModule { +trait HardwiredResetVectorModule extends HasTopLevelNetworksModule { val outer: HardwiredResetVector val io: HardwiredResetVectorBundle diff --git a/src/main/scala/rocketchip/RocketPlexMaster.scala b/src/main/scala/rocketchip/RocketPlexMaster.scala index 06591dbb..8d2bf546 100644 --- a/src/main/scala/rocketchip/RocketPlexMaster.scala +++ b/src/main/scala/rocketchip/RocketPlexMaster.scala @@ -10,12 +10,12 @@ import uncore.devices._ import util._ import coreplex._ -trait RocketPlexMaster extends TopNetwork { +trait RocketPlexMaster extends HasTopLevelNetworks { val module: RocketPlexMasterModule val coreplex = LazyModule(new DefaultCoreplex) - coreplex.l2in :=* l2.node + coreplex.l2in :=* l2FrontendBus.node socBus.node := coreplex.mmio coreplex.mmioInt := intBus.intnode @@ -23,11 +23,11 @@ trait RocketPlexMaster extends TopNetwork { (mem zip coreplex.mem) foreach { case (xbar, channel) => xbar.node :=* channel } } -trait RocketPlexMasterBundle extends TopNetworkBundle { +trait RocketPlexMasterBundle extends HasTopLevelNetworksBundle { val outer: RocketPlexMaster } -trait RocketPlexMasterModule extends TopNetworkModule { +trait RocketPlexMasterModule extends HasTopLevelNetworksModule { val outer: RocketPlexMaster val io: RocketPlexMasterBundle val clock: Clock diff --git a/src/main/scala/rocketchip/TestHarness.scala b/src/main/scala/rocketchip/TestHarness.scala index ab7126b4..3d50bed5 100644 --- a/src/main/scala/rocketchip/TestHarness.scala +++ b/src/main/scala/rocketchip/TestHarness.scala @@ -29,7 +29,7 @@ class TestHarness()(implicit p: Parameters) extends Module { val mmio_sim = Module(LazyModule(new SimAXIMem(1, 4096)).module) mmio_sim.io.axi4 <> dut.io.mmio_axi4 - val l2_axi4 = dut.io.l2_axi4(0) + val l2_axi4 = dut.io.l2_frontend_bus_axi4(0) l2_axi4.ar.valid := Bool(false) l2_axi4.aw.valid := Bool(false) l2_axi4.w .valid := Bool(false)