riscv/rocket-chip
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rocketchip: rename some periphery ports

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This commit is contained in:
Henry Cook
2017-02-23 14:25:17 -08:00
parent 6c3011d513
commit a281ad8ad2
7 changed files with 87 additions and 82 deletions
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2
src/main/scala/rocketchip/TestHarness.scala
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@ -29,7 +29,7 @@ class TestHarness()(implicit p: Parameters) extends Module {
val mmio_sim = Module(LazyModule(new SimAXIMem(1, 4096)).module)
mmio_sim.io.axi4 <> dut.io.mmio_axi4
val l2_axi4 = dut.io.l2_axi4(0)
val l2_axi4 = dut.io.l2_frontend_bus_axi4(0)
l2_axi4.ar.valid := Bool(false)
l2_axi4.aw.valid := Bool(false)
l2_axi4.w .valid := Bool(false)