rocketchip: rename some periphery ports
This commit is contained in:
Henry Cook
@ -37,16 +37,17 @@ case object ZeroConfig extends Field[ZeroConfig]
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/** Utility trait for quick access to some relevant parameters */
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trait HasPeripheryParameters {
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implicit val p: Parameters
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lazy val peripheryBusConfig = p(PeripheryBusConfig)
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lazy val socBusConfig = p(SOCBusConfig)
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lazy val cacheBlockBytes = p(CacheBlockBytes)
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lazy val peripheryBusArithmetic = p(PeripheryBusArithmetic)
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def peripheryBusConfig = p(PeripheryBusConfig)
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def socBusConfig = p(SOCBusConfig)
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def cacheBlockBytes = p(CacheBlockBytes)
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def peripheryBusArithmetic = p(PeripheryBusArithmetic)
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def nMemoryChannels = p(coreplex.BankedL2Config).nMemoryChannels
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}
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/////
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trait PeripheryExtInterrupts {
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this: TopNetwork =>
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this: HasTopLevelNetworks =>
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val nExtInterrupts = p(NExtTopInterrupts)
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val extInterrupts = IntInternalInputNode(nExtInterrupts)
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@ -57,14 +58,14 @@ trait PeripheryExtInterrupts {
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}
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trait PeripheryExtInterruptsBundle {
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this: TopNetworkBundle {
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this: HasTopLevelNetworksBundle {
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val outer: PeripheryExtInterrupts
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} =>
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val interrupts = UInt(INPUT, width = outer.nExtInterrupts)
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}
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trait PeripheryExtInterruptsModule {
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this: TopNetworkModule {
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this: HasTopLevelNetworksModule {
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val outer: PeripheryExtInterrupts
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val io: PeripheryExtInterruptsBundle
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} =>
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@ -74,7 +75,7 @@ trait PeripheryExtInterruptsModule {
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/////
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trait PeripheryMasterAXI4Mem {
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this: TopNetwork =>
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this: HasTopLevelNetworks =>
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val module: PeripheryMasterAXI4MemModule
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private val config = p(ExtMem)
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@ -107,14 +108,14 @@ trait PeripheryMasterAXI4Mem {
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}
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trait PeripheryMasterAXI4MemBundle {
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this: TopNetworkBundle {
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this: HasTopLevelNetworksBundle {
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val outer: PeripheryMasterAXI4Mem
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} =>
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val mem_axi4 = outer.mem_axi4.bundleOut
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}
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trait PeripheryMasterAXI4MemModule {
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this: TopNetworkModule {
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this: HasTopLevelNetworksModule {
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val outer: PeripheryMasterAXI4Mem
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val io: PeripheryMasterAXI4MemBundle
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} =>
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@ -123,7 +124,7 @@ trait PeripheryMasterAXI4MemModule {
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/////
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trait PeripheryZero {
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this: TopNetwork =>
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this: HasTopLevelNetworks =>
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val module: PeripheryZeroModule
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private val config = p(ZeroConfig)
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@ -138,13 +139,13 @@ trait PeripheryZero {
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}
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trait PeripheryZeroBundle {
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this: TopNetworkBundle {
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this: HasTopLevelNetworksBundle {
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val outer: PeripheryZero
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} =>
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}
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trait PeripheryZeroModule {
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this: TopNetworkModule {
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this: HasTopLevelNetworksModule {
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val outer: PeripheryZero
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val io: PeripheryZeroBundle
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} =>
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@ -154,7 +155,7 @@ trait PeripheryZeroModule {
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// PeripheryMasterAXI4MMIO is an example, make your own cake pattern like this one.
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trait PeripheryMasterAXI4MMIO {
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this: TopNetwork =>
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this: HasTopLevelNetworks =>
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private val config = p(ExtBus)
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val mmio_axi4 = AXI4BlindOutputNode(Seq(AXI4SlavePortParameters(
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@ -175,14 +176,14 @@ trait PeripheryMasterAXI4MMIO {
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}
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trait PeripheryMasterAXI4MMIOBundle {
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this: TopNetworkBundle {
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this: HasTopLevelNetworksBundle {
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val outer: PeripheryMasterAXI4MMIO
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} =>
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val mmio_axi4 = outer.mmio_axi4.bundleOut
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}
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trait PeripheryMasterAXI4MMIOModule {
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this: TopNetworkModule {
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this: HasTopLevelNetworksModule {
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val outer: PeripheryMasterAXI4MMIO
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val io: PeripheryMasterAXI4MMIOBundle
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} =>
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@ -192,26 +193,26 @@ trait PeripheryMasterAXI4MMIOModule {
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/////
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// PeripherySlaveAXI4 is an example, make your own cake pattern like this one.
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trait PeripherySlaveAXI4 extends TopNetwork {
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trait PeripherySlaveAXI4 extends HasTopLevelNetworks {
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private val config = p(ExtIn)
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val l2_axi4 = AXI4BlindInputNode(Seq(AXI4MasterPortParameters(
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val l2FrontendAXI4Node = AXI4BlindInputNode(Seq(AXI4MasterPortParameters(
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masters = Seq(AXI4MasterParameters(
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id = IdRange(0, 1 << config.idBits))))))
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l2.node :=
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l2FrontendBus.node :=
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TLSourceShrinker(1 << config.sourceBits)(
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TLWidthWidget(config.beatBytes)(
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AXI4ToTL()(
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AXI4Fragmenter()(
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l2_axi4))))
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l2FrontendAXI4Node))))
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}
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trait PeripherySlaveAXI4Bundle extends TopNetworkBundle {
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trait PeripherySlaveAXI4Bundle extends HasTopLevelNetworksBundle {
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val outer: PeripherySlaveAXI4
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val l2_axi4 = outer.l2_axi4.bundleIn
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val l2_frontend_bus_axi4 = outer.l2FrontendAXI4Node.bundleIn
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}
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trait PeripherySlaveAXI4Module extends TopNetworkModule {
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trait PeripherySlaveAXI4Module extends HasTopLevelNetworksModule {
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val outer: PeripherySlaveAXI4
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val io: PeripherySlaveAXI4Bundle
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// nothing to do
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@ -221,7 +222,7 @@ trait PeripherySlaveAXI4Module extends TopNetworkModule {
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// Add an external TL-UL slave
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trait PeripheryMasterTLMMIO {
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this: TopNetwork =>
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this: HasTopLevelNetworks =>
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private val config = p(ExtBus)
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val mmio_tl = TLBlindOutputNode(Seq(TLManagerPortParameters(
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@ -241,14 +242,14 @@ trait PeripheryMasterTLMMIO {
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}
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trait PeripheryMasterTLMMIOBundle {
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this: TopNetworkBundle {
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this: HasTopLevelNetworksBundle {
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val outer: PeripheryMasterTLMMIO
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} =>
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val mmio_tl = outer.mmio_tl.bundleOut
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}
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trait PeripheryMasterTLMMIOModule {
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this: TopNetworkModule {
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this: HasTopLevelNetworksModule {
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val outer: PeripheryMasterTLMMIO
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val io: PeripheryMasterTLMMIOBundle
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} =>
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@ -258,24 +259,24 @@ trait PeripheryMasterTLMMIOModule {
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/////
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// NOTE: this port is NOT allowed to issue Acquires
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trait PeripherySlaveTL extends TopNetwork {
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trait PeripherySlaveTL extends HasTopLevelNetworks {
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private val config = p(ExtIn)
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val l2_tl = TLBlindInputNode(Seq(TLClientPortParameters(
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val l2FrontendTLNode = TLBlindInputNode(Seq(TLClientPortParameters(
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clients = Seq(TLClientParameters(
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sourceId = IdRange(0, 1 << config.idBits))))))
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l2.node :=
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l2FrontendBus.node :=
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TLSourceShrinker(1 << config.sourceBits)(
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TLWidthWidget(config.beatBytes)(
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l2_tl))
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l2FrontendTLNode))
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}
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trait PeripherySlaveTLBundle extends TopNetworkBundle {
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trait PeripherySlaveTLBundle extends HasTopLevelNetworksBundle {
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val outer: PeripherySlaveTL
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val l2_tl = outer.l2_tl.bundleIn
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val l2_frontend_bus_tl = outer.l2FrontendTLNode.bundleIn
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}
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trait PeripherySlaveTLModule extends TopNetworkModule {
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trait PeripherySlaveTLModule extends HasTopLevelNetworksModule {
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val outer: PeripherySlaveTL
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val io: PeripherySlaveTLBundle
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// nothing to do
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@ -284,7 +285,7 @@ trait PeripherySlaveTLModule extends TopNetworkModule {
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/////
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trait PeripheryBootROM {
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this: TopNetwork =>
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this: HasTopLevelNetworks =>
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val coreplex: CoreplexRISCVPlatform
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private val bootrom_address = 0x1000
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@ -295,13 +296,13 @@ trait PeripheryBootROM {
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}
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trait PeripheryBootROMBundle {
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this: TopNetworkBundle {
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this: HasTopLevelNetworksBundle {
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val outer: PeripheryBootROM
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} =>
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}
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trait PeripheryBootROMModule {
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this: TopNetworkModule {
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this: HasTopLevelNetworksModule {
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val outer: PeripheryBootROM
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val io: PeripheryBootROMBundle
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} =>
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@ -310,20 +311,20 @@ trait PeripheryBootROMModule {
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/////
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trait PeripheryTestRAM {
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this: TopNetwork =>
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this: HasTopLevelNetworks =>
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val testram = LazyModule(new TLRAM(AddressSet(0x52000000, 0xfff), true, peripheryBusConfig.beatBytes))
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testram.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
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}
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trait PeripheryTestRAMBundle {
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this: TopNetworkBundle {
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this: HasTopLevelNetworksBundle {
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val outer: PeripheryTestRAM
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} =>
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}
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trait PeripheryTestRAMModule {
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this: TopNetworkModule {
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this: HasTopLevelNetworksModule {
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val outer: PeripheryTestRAM
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val io: PeripheryTestRAMBundle
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} =>
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@ -332,19 +333,19 @@ trait PeripheryTestRAMModule {
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/////
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trait PeripheryTestBusMaster {
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this: TopNetwork =>
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this: HasTopLevelNetworks =>
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val fuzzer = LazyModule(new TLFuzzer(5000))
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peripheryBus.node := fuzzer.node
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}
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trait PeripheryTestBusMasterBundle {
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this: TopNetworkBundle {
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this: HasTopLevelNetworksBundle {
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val outer: PeripheryTestBusMaster
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} =>
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}
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trait PeripheryTestBusMasterModule {
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this: TopNetworkModule {
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this: HasTopLevelNetworksModule {
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val outer: PeripheryTestBusMaster
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val io: PeripheryTestBusMasterBundle
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} =>
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