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SimJTAG: fix verilog typo

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This commit is contained in:
Megan Wachs 2018-03-05 16:27:17 -08:00
parent bd3a72e585
commit a20998e215
1 changed files with 1 additions and 1 deletions
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vsrc/SimJTAG.v
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@ -63,7 +63,7 @@ module SimJTAG #(
if (reset || r_reset) begin if (reset || r_reset) begin
__exit = 0; __exit = 0;
tickCounterReg <= TICK_DELAY; tickCounterReg <= TICK_DELAY;
init_done_sticky <= 1/b0; init_done_sticky <= 1'b0;
end else begin end else begin
init_done_sticky <= init_done | init_done_sticky; init_done_sticky <= init_done | init_done_sticky;
if (enable && init_done_sticky) begin if (enable && init_done_sticky) begin