From a20998e215429c2b6dbf115e208a2f8c0abec374 Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Mon, 5 Mar 2018 16:27:17 -0800
Subject: [PATCH] SimJTAG: fix verilog typo

---
 vsrc/SimJTAG.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/vsrc/SimJTAG.v b/vsrc/SimJTAG.v
index e7aca0af..0fec99df 100644
--- a/vsrc/SimJTAG.v
+++ b/vsrc/SimJTAG.v
@@ -63,7 +63,7 @@ module SimJTAG #(
       if (reset || r_reset) begin
          __exit = 0;
          tickCounterReg <= TICK_DELAY;
-         init_done_sticky <= 1/b0;
+         init_done_sticky <= 1'b0;
       end else begin
          init_done_sticky <= init_done | init_done_sticky;
          if (enable && init_done_sticky) begin