From a1fc01fd6d9589e710f58a4eda44f1a05d017cf4 Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Fri, 2 Sep 2016 22:41:42 -0700
Subject: [PATCH] tilelink2: prevent mapping the same register twice

---
 src/main/scala/uncore/tilelink2/RegMapper.scala | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/main/scala/uncore/tilelink2/RegMapper.scala b/src/main/scala/uncore/tilelink2/RegMapper.scala
index c6b517b5..d3f7a559 100644
--- a/src/main/scala/uncore/tilelink2/RegMapper.scala
+++ b/src/main/scala/uncore/tilelink2/RegMapper.scala
@@ -31,6 +31,11 @@ object RegMapper
     val regmap = mapping.toList
     require (!regmap.isEmpty)
 
+    // Ensure no register appears twice
+    regmap.combinations(2).foreach { case Seq((reg1, _), (reg2, _)) =>
+      require (reg1 != reg2)
+    }
+
     // Flatten the regmap into (Reg:Int, Offset:Int, field:RegField)
     val flat = regmap.map { case (reg, fields) =>
       val offsets = fields.scanLeft(0)(_ + _.width).init