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tile: add tileBus xbar

This commit is contained in:
Henry Cook 2017-05-16 16:12:01 -07:00
parent ad087dd18d
commit a19fc2549e
5 changed files with 5 additions and 3 deletions

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@ -183,7 +183,7 @@ trait HasICacheFrontend extends CanHavePTW with HasTileLinkMasterPort {
val module: HasICacheFrontendModule val module: HasICacheFrontendModule
val frontend = LazyModule(new Frontend(hartid: Int)) val frontend = LazyModule(new Frontend(hartid: Int))
val hartid: Int val hartid: Int
masterNode := frontend.masterNode tileBus.node := frontend.masterNode
nPTWPorts += 1 nPTWPorts += 1
} }

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@ -196,7 +196,7 @@ trait HasHellaCache extends HasTileLinkMasterPort with HasTileParameters {
def findScratchpadFromICache: Option[AddressSet] def findScratchpadFromICache: Option[AddressSet]
var nDCachePorts = 0 var nDCachePorts = 0
val dcache = HellaCache(tileParams.dcache.get.nMSHRs == 0, findScratchpadFromICache _) val dcache = HellaCache(tileParams.dcache.get.nMSHRs == 0, findScratchpadFromICache _)
masterNode := dcache.node tileBus.node := dcache.node
} }
trait HasHellaCacheBundle extends HasTileLinkMasterPortBundle { trait HasHellaCacheBundle extends HasTileLinkMasterPortBundle {

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@ -55,6 +55,8 @@ trait HasTileLinkMasterPort {
implicit val p: Parameters implicit val p: Parameters
val module: HasTileLinkMasterPortModule val module: HasTileLinkMasterPortModule
val masterNode = TLOutputNode() val masterNode = TLOutputNode()
val tileBus = LazyModule(new TLXbar) // TileBus xbar for cache backends to connect to
masterNode := tileBus.node
} }
trait HasTileLinkMasterPortBundle { trait HasTileLinkMasterPortBundle {

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@ -48,7 +48,7 @@ trait CanHaveLegacyRoccs extends CanHaveSharedFPU with CanHavePTW with HasTileLi
}}))) }})))
legacyRocc foreach { lr => legacyRocc foreach { lr =>
masterNode := lr.masterNode tileBus.node := lr.masterNode
nPTWPorts += lr.nPTWPorts nPTWPorts += lr.nPTWPorts
nDCachePorts += lr.nRocc nDCachePorts += lr.nRocc
} }