From a19fc2549e650cbbc9661f26dc089fabb34322c3 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Tue, 16 May 2017 16:12:01 -0700 Subject: [PATCH] tile: add tileBus xbar --- src/main/scala/rocket/Frontend.scala | 2 +- src/main/scala/rocket/HellaCache.scala | 2 +- src/main/scala/rocket/{Tile.scala => RocketTiles.scala} | 0 src/main/scala/tile/BaseTile.scala | 2 ++ src/main/scala/tile/LegacyRoCC.scala | 2 +- 5 files changed, 5 insertions(+), 3 deletions(-) rename src/main/scala/rocket/{Tile.scala => RocketTiles.scala} (100%) diff --git a/src/main/scala/rocket/Frontend.scala b/src/main/scala/rocket/Frontend.scala index c906b21e..94ef4654 100644 --- a/src/main/scala/rocket/Frontend.scala +++ b/src/main/scala/rocket/Frontend.scala @@ -183,7 +183,7 @@ trait HasICacheFrontend extends CanHavePTW with HasTileLinkMasterPort { val module: HasICacheFrontendModule val frontend = LazyModule(new Frontend(hartid: Int)) val hartid: Int - masterNode := frontend.masterNode + tileBus.node := frontend.masterNode nPTWPorts += 1 } diff --git a/src/main/scala/rocket/HellaCache.scala b/src/main/scala/rocket/HellaCache.scala index 0624fe5d..6b3ce443 100644 --- a/src/main/scala/rocket/HellaCache.scala +++ b/src/main/scala/rocket/HellaCache.scala @@ -196,7 +196,7 @@ trait HasHellaCache extends HasTileLinkMasterPort with HasTileParameters { def findScratchpadFromICache: Option[AddressSet] var nDCachePorts = 0 val dcache = HellaCache(tileParams.dcache.get.nMSHRs == 0, findScratchpadFromICache _) - masterNode := dcache.node + tileBus.node := dcache.node } trait HasHellaCacheBundle extends HasTileLinkMasterPortBundle { diff --git a/src/main/scala/rocket/Tile.scala b/src/main/scala/rocket/RocketTiles.scala similarity index 100% rename from src/main/scala/rocket/Tile.scala rename to src/main/scala/rocket/RocketTiles.scala diff --git a/src/main/scala/tile/BaseTile.scala b/src/main/scala/tile/BaseTile.scala index 3aef5be2..65f1ad2f 100644 --- a/src/main/scala/tile/BaseTile.scala +++ b/src/main/scala/tile/BaseTile.scala @@ -55,6 +55,8 @@ trait HasTileLinkMasterPort { implicit val p: Parameters val module: HasTileLinkMasterPortModule val masterNode = TLOutputNode() + val tileBus = LazyModule(new TLXbar) // TileBus xbar for cache backends to connect to + masterNode := tileBus.node } trait HasTileLinkMasterPortBundle { diff --git a/src/main/scala/tile/LegacyRoCC.scala b/src/main/scala/tile/LegacyRoCC.scala index 70b5f89a..7d052021 100644 --- a/src/main/scala/tile/LegacyRoCC.scala +++ b/src/main/scala/tile/LegacyRoCC.scala @@ -48,7 +48,7 @@ trait CanHaveLegacyRoccs extends CanHaveSharedFPU with CanHavePTW with HasTileLi }}))) legacyRocc foreach { lr => - masterNode := lr.masterNode + tileBus.node := lr.masterNode nPTWPorts += lr.nPTWPorts nDCachePorts += lr.nRocc }