tile: add tileBus xbar

2017-05-16 16:12:01 -07:00
parent ad087dd18d
commit a19fc2549e
5 changed files with 5 additions and 3 deletions
--- a/src/main/scala/tile/BaseTile.scala
+++ b/src/main/scala/tile/BaseTile.scala
@ -55,6 +55,8 @@ trait HasTileLinkMasterPort {
  implicit val p: Parameters
  val module: HasTileLinkMasterPortModule
  val masterNode = TLOutputNode()
+  val tileBus = LazyModule(new TLXbar) // TileBus xbar for cache backends to connect to
+  masterNode := tileBus.node
 }

 trait HasTileLinkMasterPortBundle {