tile: add tileBus xbar

src/main/scala/tile/BaseTile.scala

@@ -55,6 +55,8 @@ trait HasTileLinkMasterPort {
   implicit val p: Parameters
   val module: HasTileLinkMasterPortModule
   val masterNode = TLOutputNode()
+  val tileBus = LazyModule(new TLXbar) // TileBus xbar for cache backends to connect to
+  masterNode := tileBus.node
 }
 
 trait HasTileLinkMasterPortBundle {

src/main/scala/tile/LegacyRoCC.scala

@@ -48,7 +48,7 @@ trait CanHaveLegacyRoccs extends CanHaveSharedFPU with CanHavePTW with HasTileLi
     }})))
 
   legacyRocc foreach { lr =>
-    masterNode := lr.masterNode
+    tileBus.node := lr.masterNode
     nPTWPorts += lr.nPTWPorts
     nDCachePorts += lr.nRocc
   }