From a10d058e1a2dd98a9ab6ecf62d1b92018cab4212 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Mon, 12 Sep 2016 18:25:35 -0700 Subject: [PATCH] fix warnings in verilog source (#274) --- vsrc/DebugTransportModuleJtag.v | 4 ++-- vsrc/jtag_vpi.v | 4 ---- 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/vsrc/DebugTransportModuleJtag.v b/vsrc/DebugTransportModuleJtag.v index 0c8a07b0..7c9b81c7 100755 --- a/vsrc/DebugTransportModuleJtag.v +++ b/vsrc/DebugTransportModuleJtag.v @@ -125,8 +125,8 @@ module DebugTransportModuleJtag ( assign idcode = {JTAG_VERSION, JTAG_PART_NUM, JTAG_MANUF_ID, 1'h1}; - wire [3:0] debugAddrBits = DEBUG_ADDR_BITS; - wire [3:0] debugVersion = DEBUG_VERSION; + wire [3:0] debugAddrBits = DEBUG_ADDR_BITS[3:0]; + wire [3:0] debugVersion = DEBUG_VERSION[3:0]; assign dtminfo = {24'b0, debugAddrBits, debugVersion}; diff --git a/vsrc/jtag_vpi.v b/vsrc/jtag_vpi.v index c7eb55d7..50afac9b 100644 --- a/vsrc/jtag_vpi.v +++ b/vsrc/jtag_vpi.v @@ -76,10 +76,6 @@ reg [31:0] data_in; integer debug; -assign tms_o = tms; -assign tck_o = tck; -assign tdi_o = tdi; - initial begin tck <= #TP 1'b0;