riscv/rocket-chip
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remove I$ prefetcher for now

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there's a bug in it, and I don't have time to fix it at the moment.
This commit is contained in:
Andrew Waterman 2012-03-27 15:43:56 -07:00
parent 452876af37
commit a09e8d1c55
1 changed files with 1 additions and 4 deletions
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rocket/src/main/scala/tile.scala
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@ -13,12 +13,11 @@ class Tile extends Component
val cpu = new rocketProc(resetSignal = io.host.reset) val cpu = new rocketProc(resetSignal = io.host.reset)
val icache = new rocketICache(128, 4) // 128 sets x 4 ways (32KB) val icache = new rocketICache(128, 4) // 128 sets x 4 ways (32KB)
val icache_pf = new rocketIPrefetcher
val dcache = new HellaCacheUniproc val dcache = new HellaCacheUniproc
val arbiter = new rocketMemArbiter(2 + (if (HAVE_VEC) 1 else 0)) val arbiter = new rocketMemArbiter(2 + (if (HAVE_VEC) 1 else 0))
arbiter.io.requestor(0) <> dcache.io.mem arbiter.io.requestor(0) <> dcache.io.mem
arbiter.io.requestor(1) <> icache_pf.io.mem arbiter.io.requestor(1) <> icache.io.mem
io.tilelink.xact_init <> Queue(arbiter.io.mem.xact_init) io.tilelink.xact_init <> Queue(arbiter.io.mem.xact_init)
io.tilelink.xact_init_data <> Queue(dcache.io.mem.xact_init_data) io.tilelink.xact_init_data <> Queue(dcache.io.mem.xact_init_data)
@ -38,8 +37,6 @@ class Tile extends Component
cpu.io.host <> io.host cpu.io.host <> io.host
icache_pf.io.invalidate := cpu.io.imem.invalidate
icache.io.mem <> icache_pf.io.icache
cpu.io.imem <> icache.io.cpu cpu.io.imem <> icache.io.cpu
cpu.io.dmem <> dcache.io.cpu cpu.io.dmem <> dcache.io.cpu
} }