From a09e8d1c5550efd2a8ed8f1861d8ed65ba342c2e Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Tue, 27 Mar 2012 15:43:56 -0700 Subject: [PATCH] remove I$ prefetcher for now there's a bug in it, and I don't have time to fix it at the moment. --- rocket/src/main/scala/tile.scala | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/rocket/src/main/scala/tile.scala b/rocket/src/main/scala/tile.scala index 2ebabc7d..1b7f6e05 100644 --- a/rocket/src/main/scala/tile.scala +++ b/rocket/src/main/scala/tile.scala @@ -13,12 +13,11 @@ class Tile extends Component val cpu = new rocketProc(resetSignal = io.host.reset) val icache = new rocketICache(128, 4) // 128 sets x 4 ways (32KB) - val icache_pf = new rocketIPrefetcher val dcache = new HellaCacheUniproc val arbiter = new rocketMemArbiter(2 + (if (HAVE_VEC) 1 else 0)) arbiter.io.requestor(0) <> dcache.io.mem - arbiter.io.requestor(1) <> icache_pf.io.mem + arbiter.io.requestor(1) <> icache.io.mem io.tilelink.xact_init <> Queue(arbiter.io.mem.xact_init) io.tilelink.xact_init_data <> Queue(dcache.io.mem.xact_init_data) @@ -38,8 +37,6 @@ class Tile extends Component cpu.io.host <> io.host - icache_pf.io.invalidate := cpu.io.imem.invalidate - icache.io.mem <> icache_pf.io.icache cpu.io.imem <> icache.io.cpu cpu.io.dmem <> dcache.io.cpu }