From 9f0fda01b33f9822d5b91b94dbc5c48b05d51f13 Mon Sep 17 00:00:00 2001 From: Scott Johnson Date: Wed, 19 Oct 2016 13:18:17 -0700 Subject: [PATCH] Fix Cadence Incisive compile warning The SystemVerilog LRM (IEEE 1800-2012) clause 20.15.1 ($random function) says: "The seed argument shall be an integral variable." This fixes the following compile warning: rand_value = $random($urandom); | ncelab: *W,WRNOTL (/home/scottj/rocket-chip/vsrc/TestDriver.v,34|23): Argument to out parameter is not a legal lvalue. --- vsrc/TestDriver.v | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/vsrc/TestDriver.v b/vsrc/TestDriver.v index 554480d2..cb98f8ac 100644 --- a/vsrc/TestDriver.v +++ b/vsrc/TestDriver.v @@ -25,13 +25,14 @@ module TestDriver; void'($value$plusargs("max-cycles=%d", max_cycles)); verbose = $test$plusargs("verbose"); - // do not delete the line below. + // do not delete the lines below. // $random function needs to be called with the seed once to affect all // the downstream $random functions within the Chisel-generated Verilog // code. // $urandom is seeded via cmdline (+ntb_random_seed in VCS) but that // doesn't seed $random. - rand_value = $random($urandom); + rand_value = $urandom; + rand_value = $random(rand_value); if (verbose) begin $fdisplay(stderr, "testing $random %0x", rand_value); end