riscv/rocket-chip
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add DRAMSideLLCNull

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Yunsup Lee 2013-03-19 00:43:34 -07:00
parent c6695bee7c
commit 9efe71412f
3 changed files with 3 additions and 2 deletions
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2
riscv-rocket

@ -1 +1 @@
Subproject commit be69e6ce1db5d00a5ccb13603c08d4cefb3f7eed Subproject commit 76cb0d00d540d5336dd9871bb7556fc1b42a4d85

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src/main/scala/RocketChip.scala
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@ -220,6 +220,7 @@ class OuterMemorySystem(htif_width: Int, tileEndpoints: Seq[ClientCoherenceAgent
val llc_tag_leaf = Mem(1024, seqRead = true) { Bits(width = 72) } val llc_tag_leaf = Mem(1024, seqRead = true) { Bits(width = 72) }
val llc_data_leaf = Mem(4096, seqRead = true) { Bits(width = 64) } val llc_data_leaf = Mem(4096, seqRead = true) { Bits(width = 64) }
val llc = new DRAMSideLLC(512, 8, 4, llc_tag_leaf, llc_data_leaf) val llc = new DRAMSideLLC(512, 8, 4, llc_tag_leaf, llc_data_leaf)
//val llc = new DRAMSideLLCNull(NGLOBAL_XACTS, REFILL_CYCLES)
val mem_serdes = new MemSerdes(htif_width) val mem_serdes = new MemSerdes(htif_width)
val hub = new CoherenceHubBroadcast()(chWithHtifConf) val hub = new CoherenceHubBroadcast()(chWithHtifConf)

2
uncore

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Subproject commit 716d708544cb8a0b37546bcd1f06e3dcd54beb0f Subproject commit bf8c0b248a0ba912aeda50102f28927aec0d5e08