From 9efe71412ff7e84eb0377ca9ee4df7fbb76c376b Mon Sep 17 00:00:00 2001
From: Yunsup Lee <yunsup@cs.berkeley.edu>
Date: Tue, 19 Mar 2013 00:43:34 -0700
Subject: [PATCH] add DRAMSideLLCNull

---
 riscv-rocket                    | 2 +-
 src/main/scala/RocketChip.scala | 1 +
 uncore                          | 2 +-
 3 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/riscv-rocket b/riscv-rocket
index be69e6ce..76cb0d00 160000
--- a/riscv-rocket
+++ b/riscv-rocket
@@ -1 +1 @@
-Subproject commit be69e6ce1db5d00a5ccb13603c08d4cefb3f7eed
+Subproject commit 76cb0d00d540d5336dd9871bb7556fc1b42a4d85
diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index 20dbc8a2..3976c2c5 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -220,6 +220,7 @@ class OuterMemorySystem(htif_width: Int, tileEndpoints: Seq[ClientCoherenceAgent
   val llc_tag_leaf = Mem(1024, seqRead = true) { Bits(width = 72) }
   val llc_data_leaf = Mem(4096, seqRead = true) { Bits(width = 64) }
   val llc = new DRAMSideLLC(512, 8, 4, llc_tag_leaf, llc_data_leaf)
+  //val llc = new DRAMSideLLCNull(NGLOBAL_XACTS, REFILL_CYCLES)
   val mem_serdes = new MemSerdes(htif_width)
 
   val hub = new CoherenceHubBroadcast()(chWithHtifConf)
diff --git a/uncore b/uncore
index 716d7085..bf8c0b24 160000
--- a/uncore
+++ b/uncore
@@ -1 +1 @@
-Subproject commit 716d708544cb8a0b37546bcd1f06e3dcd54beb0f
+Subproject commit bf8c0b248a0ba912aeda50102f28927aec0d5e08