riscv/rocket-chip
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add DRAMSideLLCNull

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Yunsup Lee
2013-03-19 00:43:34 -07:00
parent c6695bee7c
commit 9efe71412f
3 changed files with 3 additions and 2 deletions
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src/main/scala/RocketChip.scala
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@@ -220,6 +220,7 @@ class OuterMemorySystem(htif_width: Int, tileEndpoints: Seq[ClientCoherenceAgent
val llc_tag_leaf = Mem(1024, seqRead = true) { Bits(width = 72) }
val llc_data_leaf = Mem(4096, seqRead = true) { Bits(width = 64) }
val llc = new DRAMSideLLC(512, 8, 4, llc_tag_leaf, llc_data_leaf)
//val llc = new DRAMSideLLCNull(NGLOBAL_XACTS, REFILL_CYCLES)
val mem_serdes = new MemSerdes(htif_width)
val hub = new CoherenceHubBroadcast()(chWithHtifConf)