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fix Bufferless irel_vs_iacq_conflict signal

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Howard Mao 2016-07-18 17:38:20 -07:00
parent e5cccc0526
commit 9eeb1112d4
1 changed files with 6 additions and 5 deletions
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11
uncore/src/main/scala/agents/Bufferless.scala
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@ -30,13 +30,15 @@ class BufferlessBroadcastHub(implicit p: Parameters) extends HierarchicalCoheren
outer_arb.io.in <> outerList outer_arb.io.in <> outerList
io.outer <> outer_arb.io.out io.outer <> outer_arb.io.out
val iacq = Queue(io.inner.acquire, 1, pipe=true)
val irel = Queue(io.inner.release, 1, pipe=true)
// Handle acquire transaction initiation // Handle acquire transaction initiation
val irel_vs_iacq_conflict = val irel_vs_iacq_conflict =
io.inner.acquire.valid && iacq.valid &&
io.inner.release.valid && irel.valid &&
io.irel().conflicts(io.iacq()) irel.bits.conflicts(iacq.bits)
val iacq = Queue(io.inner.acquire, 1, pipe=true)
doInputRoutingWithAllocation( doInputRoutingWithAllocation(
in = iacq, in = iacq,
outs = trackerList.map(_.io.inner.acquire), outs = trackerList.map(_.io.inner.acquire),
@ -48,7 +50,6 @@ class BufferlessBroadcastHub(implicit p: Parameters) extends HierarchicalCoheren
} }
// Handle releases, which might be voluntary and might have data // Handle releases, which might be voluntary and might have data
val irel = Queue(io.inner.release, 1, pipe=true)
doInputRoutingWithAllocation( doInputRoutingWithAllocation(
in = irel, in = irel,
outs = trackerList.map(_.io.inner.release), outs = trackerList.map(_.io.inner.release),