From 9eeb1112d42cb96ce30ce8f5f38587c4a734cd60 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Mon, 18 Jul 2016 17:38:20 -0700 Subject: [PATCH] fix Bufferless irel_vs_iacq_conflict signal --- uncore/src/main/scala/agents/Bufferless.scala | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/uncore/src/main/scala/agents/Bufferless.scala b/uncore/src/main/scala/agents/Bufferless.scala index e108ca72..7c67edc4 100644 --- a/uncore/src/main/scala/agents/Bufferless.scala +++ b/uncore/src/main/scala/agents/Bufferless.scala @@ -30,13 +30,15 @@ class BufferlessBroadcastHub(implicit p: Parameters) extends HierarchicalCoheren outer_arb.io.in <> outerList io.outer <> outer_arb.io.out + val iacq = Queue(io.inner.acquire, 1, pipe=true) + val irel = Queue(io.inner.release, 1, pipe=true) + // Handle acquire transaction initiation val irel_vs_iacq_conflict = - io.inner.acquire.valid && - io.inner.release.valid && - io.irel().conflicts(io.iacq()) + iacq.valid && + irel.valid && + irel.bits.conflicts(iacq.bits) - val iacq = Queue(io.inner.acquire, 1, pipe=true) doInputRoutingWithAllocation( in = iacq, outs = trackerList.map(_.io.inner.acquire), @@ -48,7 +50,6 @@ class BufferlessBroadcastHub(implicit p: Parameters) extends HierarchicalCoheren } // Handle releases, which might be voluntary and might have data - val irel = Queue(io.inner.release, 1, pipe=true) doInputRoutingWithAllocation( in = irel, outs = trackerList.map(_.io.inner.release),