riscv/rocket-chip
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Add provisional breakpoint support

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This commit is contained in:
Andrew Waterman 2016-06-08 20:21:21 -07:00
parent 73ed4ea07b
commit 9e86b9efc9
7 changed files with 7 additions and 6 deletions
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2
chisel3

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Subproject commit dc2175b0ebafbbb4b67bcb1e9b92b639b02b36bb
Subproject commit 07fa5622ccc995f925d6d967d2a386540c9064cc

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firrtl

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Subproject commit 26694d3496b7b500a3448599eb889126335b031f
Subproject commit cc4e7e39ebad106ff72f7ac97dcdc99048ee5347

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riscv-tools

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Subproject commit 0a12a54524dba399cacc2955dc3489d8cda58740
Subproject commit e9506ebc9863c15b18eff91df870969c7464a3f0

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rocket

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Subproject commit 40e8179ba5ceac3bbce8ec11429a101ceaed61ae
Subproject commit 3fbedf65e9977b6100c52ea2c2f13042721f5f88

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src/main/scala/Configs.scala
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@ -203,6 +203,7 @@ class BaseConfig extends Config (
case UseVM => true
case UseUser => true
case UseDebug => true
case NBreakpoints => 1
case UsePerfCounters => true
case FastLoadWord => true
case FastLoadByte => false

2
src/main/scala/Testing.scala
View File

@ -109,7 +109,7 @@ object DefaultTestSuites {
val rv32siNames = LinkedHashSet("csr", "ma_fetch", "scall", "sbreak", "wfi")
val rv32si = new AssemblyTestSuite("rv32si", "rv32si", rv32siNames)(_)
val rv32miNames = LinkedHashSet("csr", "mcsr", "dirty", "illegal", "ma_addr", "ma_fetch", "sbreak", "scall")
val rv32miNames = LinkedHashSet("breakpoint", "csr", "mcsr", "dirty", "illegal", "ma_addr", "ma_fetch", "sbreak", "scall")
val rv32mi = new AssemblyTestSuite("rv32mi", "rv32mi", rv32miNames)(_)
val rv32u = List(rv32ui, rv32um)

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uncore

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Subproject commit 2929d5384c54549d9af529643d2d4d61f9df626f
Subproject commit 7aa159d223b21995de8b9381c114cc340439b26f