From 9e86b9efc9859c52d4fd3133ca0b9b518486bca5 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Wed, 8 Jun 2016 20:21:21 -0700
Subject: [PATCH] Add provisional breakpoint support

---
 chisel3                      | 2 +-
 firrtl                       | 2 +-
 riscv-tools                  | 2 +-
 rocket                       | 2 +-
 src/main/scala/Configs.scala | 1 +
 src/main/scala/Testing.scala | 2 +-
 uncore                       | 2 +-
 7 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/chisel3 b/chisel3
index dc2175b0..07fa5622 160000
--- a/chisel3
+++ b/chisel3
@@ -1 +1 @@
-Subproject commit dc2175b0ebafbbb4b67bcb1e9b92b639b02b36bb
+Subproject commit 07fa5622ccc995f925d6d967d2a386540c9064cc
diff --git a/firrtl b/firrtl
index 26694d34..cc4e7e39 160000
--- a/firrtl
+++ b/firrtl
@@ -1 +1 @@
-Subproject commit 26694d3496b7b500a3448599eb889126335b031f
+Subproject commit cc4e7e39ebad106ff72f7ac97dcdc99048ee5347
diff --git a/riscv-tools b/riscv-tools
index 0a12a545..e9506ebc 160000
--- a/riscv-tools
+++ b/riscv-tools
@@ -1 +1 @@
-Subproject commit 0a12a54524dba399cacc2955dc3489d8cda58740
+Subproject commit e9506ebc9863c15b18eff91df870969c7464a3f0
diff --git a/rocket b/rocket
index 40e8179b..3fbedf65 160000
--- a/rocket
+++ b/rocket
@@ -1 +1 @@
-Subproject commit 40e8179ba5ceac3bbce8ec11429a101ceaed61ae
+Subproject commit 3fbedf65e9977b6100c52ea2c2f13042721f5f88
diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala
index 2347a0b6..d7402e28 100644
--- a/src/main/scala/Configs.scala
+++ b/src/main/scala/Configs.scala
@@ -203,6 +203,7 @@ class BaseConfig extends Config (
       case UseVM => true
       case UseUser => true
       case UseDebug => true
+      case NBreakpoints => 1
       case UsePerfCounters => true
       case FastLoadWord => true
       case FastLoadByte => false
diff --git a/src/main/scala/Testing.scala b/src/main/scala/Testing.scala
index 97b4b496..01e56c82 100644
--- a/src/main/scala/Testing.scala
+++ b/src/main/scala/Testing.scala
@@ -109,7 +109,7 @@ object DefaultTestSuites {
   val rv32siNames = LinkedHashSet("csr", "ma_fetch", "scall", "sbreak", "wfi")
   val rv32si = new AssemblyTestSuite("rv32si", "rv32si", rv32siNames)(_)
 
-  val rv32miNames = LinkedHashSet("csr", "mcsr", "dirty", "illegal", "ma_addr", "ma_fetch", "sbreak", "scall")
+  val rv32miNames = LinkedHashSet("breakpoint", "csr", "mcsr", "dirty", "illegal", "ma_addr", "ma_fetch", "sbreak", "scall")
   val rv32mi = new AssemblyTestSuite("rv32mi", "rv32mi", rv32miNames)(_)
 
   val rv32u = List(rv32ui, rv32um)
diff --git a/uncore b/uncore
index 2929d538..7aa159d2 160000
--- a/uncore
+++ b/uncore
@@ -1 +1 @@
-Subproject commit 2929d5384c54549d9af529643d2d4d61f9df626f
+Subproject commit 7aa159d223b21995de8b9381c114cc340439b26f