riscv/rocket-chip
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Remove HTIF port

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This commit is contained in:
Andrew Waterman 2016-05-03 13:41:58 -07:00
parent 5352497edb
commit 9dd23a603a
1 changed files with 0 additions and 6 deletions
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6
rocket/src/main/scala/tile.scala
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@ -30,7 +30,6 @@ abstract class Tile(resetSignal: Bool = null)
val io = new Bundle { val io = new Bundle {
val cached = Vec(nCachedTileLinkPorts, new ClientTileLinkIO) val cached = Vec(nCachedTileLinkPorts, new ClientTileLinkIO)
val uncached = Vec(nUncachedTileLinkPorts, new ClientUncachedTileLinkIO) val uncached = Vec(nUncachedTileLinkPorts, new ClientUncachedTileLinkIO)
val host = new HtifIO // Unused, but temporarily extant for zscale/groundtest
val prci = new PRCITileIO().flip val prci = new PRCITileIO().flip
val dma = new DmaIO val dma = new DmaIO
} }
@ -142,9 +141,4 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(
fpu.io.cp_resp.ready := Bool(false) fpu.io.cp_resp.ready := Bool(false)
} }
} }
// TODO remove
io.host.csr.resp.valid := io.host.csr.req.valid
io.host.csr.req.ready := io.host.csr.resp.ready
io.host.csr.resp.bits := UInt(0)
} }