From 9dd23a603ae79b0f9d1efad7571acb24a0b4bcef Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Tue, 3 May 2016 13:41:58 -0700 Subject: [PATCH] Remove HTIF port --- rocket/src/main/scala/tile.scala | 6 ------ 1 file changed, 6 deletions(-) diff --git a/rocket/src/main/scala/tile.scala b/rocket/src/main/scala/tile.scala index 4312fc47..dd88f993 100644 --- a/rocket/src/main/scala/tile.scala +++ b/rocket/src/main/scala/tile.scala @@ -30,7 +30,6 @@ abstract class Tile(resetSignal: Bool = null) val io = new Bundle { val cached = Vec(nCachedTileLinkPorts, new ClientTileLinkIO) val uncached = Vec(nUncachedTileLinkPorts, new ClientUncachedTileLinkIO) - val host = new HtifIO // Unused, but temporarily extant for zscale/groundtest val prci = new PRCITileIO().flip val dma = new DmaIO } @@ -142,9 +141,4 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile( fpu.io.cp_resp.ready := Bool(false) } } - - // TODO remove - io.host.csr.resp.valid := io.host.csr.req.valid - io.host.csr.req.ready := io.host.csr.resp.ready - io.host.csr.resp.bits := UInt(0) }