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ahb: don't violate spec with SRAM fuzzing

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This commit is contained in:
Wesley W. Terpstra 2016-12-14 14:53:54 -08:00
parent 1a0021b818
commit 9d50704b64
1 changed files with 6 additions and 1 deletions
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7
src/main/scala/uncore/ahb/SRAM.scala
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@ -91,8 +91,13 @@ class AHBRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4
val muxdata = Vec((p_mask.toBools zip (p_wdata zip d_rdata)) val muxdata = Vec((p_mask.toBools zip (p_wdata zip d_rdata))
map { case (m, (p, r)) => Mux(d_bypass && m, p, r) }) map { case (m, (p, r)) => Mux(d_bypass && m, p, r) })
// Don't fuzz hready when not in data phase
val d_request = Reg(Bool(false))
when (in.hready) { d_request := Bool(false) }
when (a_request) { d_request := Bool(true) }
// Finally, the outputs // Finally, the outputs
in.hreadyout := LFSR16(Bool(true))(0) // Bool(true) in.hreadyout := !d_request || LFSR16(Bool(true))(0) // Bool(true)
in.hresp := AHBParameters.RESP_OKAY in.hresp := AHBParameters.RESP_OKAY
in.hrdata := Mux(in.hreadyout, muxdata.asUInt, UInt(0)) in.hrdata := Mux(in.hreadyout, muxdata.asUInt, UInt(0))
} }