riscv/rocket-chip
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added HasAddrMapParameters and GlobalAddrMap

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This commit is contained in:
Henry Cook
2015-10-06 18:24:08 -07:00
parent 1c489d75c1
commit 9d11b64c75
5 changed files with 12 additions and 11 deletions
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2
junctions

Submodule junctions updated: 790f01f9e5...55471be1a8

2
rocket

Submodule rocket updated: dcc32b8e6e...3ced30fd6a

2
src/main/scala/Configs.scala
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@ -169,7 +169,7 @@ class DefaultConfig extends ChiselConfig (
case UseBackupMemoryPort => true case UseBackupMemoryPort => true
case MMIOBase => BigInt(1 << 30) // 1 GB case MMIOBase => BigInt(1 << 30) // 1 GB
case ExternalIOStart => 2 * site(MMIOBase) case ExternalIOStart => 2 * site(MMIOBase)
case NastiAddrMap => AddrMap( case GlobalAddrMap => AddrMap(
AddrMapEntry("mem", None, MemSize(site(MMIOBase), AddrMapConsts.RWX)), AddrMapEntry("mem", None, MemSize(site(MMIOBase), AddrMapConsts.RWX)),
AddrMapEntry("conf", None, MemSubmap(site(ExternalIOStart) - site(MMIOBase), genCsrAddrMap)), AddrMapEntry("conf", None, MemSubmap(site(ExternalIOStart) - site(MMIOBase), genCsrAddrMap)),
AddrMapEntry("io", Some(site(ExternalIOStart)), MemSize(2 * site(MMIOBase), AddrMapConsts.RW))) AddrMapEntry("io", Some(site(ExternalIOStart)), MemSize(2 * site(MMIOBase), AddrMapConsts.RW)))

15
src/main/scala/RocketChip.scala
View File

@ -224,16 +224,17 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
val outerTLParams = p.alterPartial({ case TLId => "L2ToMC" }) val outerTLParams = p.alterPartial({ case TLId => "L2ToMC" })
val backendBuffering = TileLinkDepths(0,0,0,0,0) val backendBuffering = TileLinkDepths(0,0,0,0,0)
val addrMap = new AddrHashMap(p(NastiAddrMap)) val addrMap = p(GlobalAddrMap)
val addrHashMap = new AddrHashMap(addrMap)
val nMasters = managerEndpoints.size + 1 val nMasters = managerEndpoints.size + 1
val nSlaves = addrMap.nEntries val nSlaves = addrHashMap.nEntries
println("Generated Address Map") println("Generated Address Map")
for ((name, base, size, _) <- addrMap.sortedEntries) { for ((name, base, size, _) <- addrHashMap.sortedEntries) {
println(f"\t$name%s $base%x - ${base + size - 1}%x") println(f"\t$name%s $base%x - ${base + size - 1}%x")
} }
val interconnect = Module(new NastiTopInterconnect(nMasters, nSlaves)(p)) val interconnect = Module(new NastiTopInterconnect(nMasters, nSlaves, addrMap)(p))
for ((bank, i) <- managerEndpoints.zipWithIndex) { for ((bank, i) <- managerEndpoints.zipWithIndex) {
val unwrap = Module(new ClientTileLinkIOUnwrapper()(outerTLParams)) val unwrap = Module(new ClientTileLinkIOUnwrapper()(outerTLParams))
@ -248,17 +249,17 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
for (i <- 0 until nTiles) { for (i <- 0 until nTiles) {
val csrName = s"conf:csr$i" val csrName = s"conf:csr$i"
val csrPort = addrMap(csrName).port val csrPort = addrHashMap(csrName).port
val conv = Module(new SMIIONastiIOConverter(xLen, csrAddrBits)) val conv = Module(new SMIIONastiIOConverter(xLen, csrAddrBits))
conv.io.nasti <> interconnect.io.slaves(csrPort) conv.io.nasti <> interconnect.io.slaves(csrPort)
io.csr(i) <> conv.io.smi io.csr(i) <> conv.io.smi
} }
val conv = Module(new SMIIONastiIOConverter(scrDataBits, scrAddrBits)) val conv = Module(new SMIIONastiIOConverter(scrDataBits, scrAddrBits))
conv.io.nasti <> interconnect.io.slaves(addrMap("conf:scr").port) conv.io.nasti <> interconnect.io.slaves(addrHashMap("conf:scr").port)
io.scr <> conv.io.smi io.scr <> conv.io.smi
io.mmio <> interconnect.io.slaves(addrMap("io").port) io.mmio <> interconnect.io.slaves(addrHashMap("io").port)
val mem_channels = interconnect.io.slaves.take(nMemChannels) val mem_channels = interconnect.io.slaves.take(nMemChannels)

2
uncore

Submodule uncore updated: c824028e4f...69e494348c