diff --git a/junctions b/junctions
index 790f01f9..55471be1 160000
--- a/junctions
+++ b/junctions
@@ -1 +1 @@
-Subproject commit 790f01f9e5df6d9d3ecaf636ccb95d1eb751879d
+Subproject commit 55471be1a864f606c2961680ff90fa8ca6457441
diff --git a/rocket b/rocket
index dcc32b8e..3ced30fd 160000
--- a/rocket
+++ b/rocket
@@ -1 +1 @@
-Subproject commit dcc32b8e6eb3b62962db952bba2e34c36137523e
+Subproject commit 3ced30fd6a4686751e2218c5b268c099851dd179
diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala
index d6ff592f..348ec2f2 100644
--- a/src/main/scala/Configs.scala
+++ b/src/main/scala/Configs.scala
@@ -169,7 +169,7 @@ class DefaultConfig extends ChiselConfig (
       case UseBackupMemoryPort => true
       case MMIOBase => BigInt(1 << 30) // 1 GB
       case ExternalIOStart => 2 * site(MMIOBase)
-      case NastiAddrMap => AddrMap(
+      case GlobalAddrMap => AddrMap(
         AddrMapEntry("mem", None, MemSize(site(MMIOBase), AddrMapConsts.RWX)),
         AddrMapEntry("conf", None, MemSubmap(site(ExternalIOStart) - site(MMIOBase), genCsrAddrMap)),
         AddrMapEntry("io", Some(site(ExternalIOStart)), MemSize(2 * site(MMIOBase), AddrMapConsts.RW)))
diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index fa5b5a95..f8306d44 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -224,16 +224,17 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
   val outerTLParams = p.alterPartial({ case TLId => "L2ToMC" })
   val backendBuffering = TileLinkDepths(0,0,0,0,0)
 
-  val addrMap = new AddrHashMap(p(NastiAddrMap))
+  val addrMap = p(GlobalAddrMap)
+  val addrHashMap = new AddrHashMap(addrMap)
   val nMasters = managerEndpoints.size + 1
-  val nSlaves = addrMap.nEntries
+  val nSlaves = addrHashMap.nEntries
 
   println("Generated Address Map")
-  for ((name, base, size, _) <- addrMap.sortedEntries) {
+  for ((name, base, size, _) <- addrHashMap.sortedEntries) {
     println(f"\t$name%s $base%x - ${base + size - 1}%x")
   }
 
-  val interconnect = Module(new NastiTopInterconnect(nMasters, nSlaves)(p))
+  val interconnect = Module(new NastiTopInterconnect(nMasters, nSlaves, addrMap)(p))
 
   for ((bank, i) <- managerEndpoints.zipWithIndex) {
     val unwrap = Module(new ClientTileLinkIOUnwrapper()(outerTLParams))
@@ -248,17 +249,17 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
 
   for (i <- 0 until nTiles) {
     val csrName = s"conf:csr$i"
-    val csrPort = addrMap(csrName).port
+    val csrPort = addrHashMap(csrName).port
     val conv = Module(new SMIIONastiIOConverter(xLen, csrAddrBits))
     conv.io.nasti <> interconnect.io.slaves(csrPort)
     io.csr(i) <> conv.io.smi
   }
 
   val conv = Module(new SMIIONastiIOConverter(scrDataBits, scrAddrBits))
-  conv.io.nasti <> interconnect.io.slaves(addrMap("conf:scr").port)
+  conv.io.nasti <> interconnect.io.slaves(addrHashMap("conf:scr").port)
   io.scr <> conv.io.smi
 
-  io.mmio <> interconnect.io.slaves(addrMap("io").port)
+  io.mmio <> interconnect.io.slaves(addrHashMap("io").port)
 
   val mem_channels = interconnect.io.slaves.take(nMemChannels)
 
diff --git a/uncore b/uncore
index c824028e..69e49434 160000
--- a/uncore
+++ b/uncore
@@ -1 +1 @@
-Subproject commit c824028e4f38006058ae0757a5339e3273e0ee2b
+Subproject commit 69e494348c2b3ea7ff3abed392fcff2fb7cf730c