riscv/rocket-chip
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example Rocc accelerator fixes

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This commit is contained in:
Howard Mao 2016-08-04 11:17:13 -07:00
parent 410e3e5366
commit 9c4e57aea5
1 changed files with 2 additions and 5 deletions
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7
rocket/src/main/scala/rocc.scala
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@ -94,6 +94,7 @@ class AccumulatorExample(n: Int = 4)(implicit p: Parameters) extends RoCC()(p) {
when (io.mem.resp.valid) { when (io.mem.resp.valid) {
regfile(memRespTag) := io.mem.resp.bits.data regfile(memRespTag) := io.mem.resp.bits.data
busy(memRespTag) := Bool(false)
} }
// control // control
@ -101,10 +102,6 @@ class AccumulatorExample(n: Int = 4)(implicit p: Parameters) extends RoCC()(p) {
busy(addr) := Bool(true) busy(addr) := Bool(true)
} }
when (io.mem.resp.valid) {
busy(memRespTag) := Bool(false)
}
val doResp = cmd.bits.inst.xd val doResp = cmd.bits.inst.xd
val stallReg = busy(addr) val stallReg = busy(addr)
val stallLoad = doLoad && !io.mem.req.ready val stallLoad = doLoad && !io.mem.req.ready
@ -175,7 +172,7 @@ class TranslatorExample(implicit p: Parameters) extends RoCC()(p) {
io.resp.valid := (state === s_resp) io.resp.valid := (state === s_resp)
io.resp.bits.rd := req_rd io.resp.bits.rd := req_rd
io.resp.bits.data := Mux(pte.leaf(), Cat(pte.ppn, req_offset), ~UInt(0, xLen)) io.resp.bits.data := Mux(pte.leaf(), Cat(pte.ppn, req_offset), SInt(-1, xLen).asUInt)
io.busy := (state =/= s_idle) io.busy := (state =/= s_idle)
io.interrupt := Bool(false) io.interrupt := Bool(false)