diff --git a/rocket/src/main/scala/rocc.scala b/rocket/src/main/scala/rocc.scala
index ce0fcfbe..a58dcd30 100644
--- a/rocket/src/main/scala/rocc.scala
+++ b/rocket/src/main/scala/rocc.scala
@@ -94,6 +94,7 @@ class AccumulatorExample(n: Int = 4)(implicit p: Parameters) extends RoCC()(p) {
 
   when (io.mem.resp.valid) {
     regfile(memRespTag) := io.mem.resp.bits.data
+    busy(memRespTag) := Bool(false)
   }
 
   // control
@@ -101,10 +102,6 @@ class AccumulatorExample(n: Int = 4)(implicit p: Parameters) extends RoCC()(p) {
     busy(addr) := Bool(true)
   }
 
-  when (io.mem.resp.valid) {
-    busy(memRespTag) := Bool(false)
-  }
-
   val doResp = cmd.bits.inst.xd
   val stallReg = busy(addr)
   val stallLoad = doLoad && !io.mem.req.ready
@@ -175,7 +172,7 @@ class TranslatorExample(implicit p: Parameters) extends RoCC()(p) {
 
   io.resp.valid := (state === s_resp)
   io.resp.bits.rd := req_rd
-  io.resp.bits.data := Mux(pte.leaf(), Cat(pte.ppn, req_offset), ~UInt(0, xLen))
+  io.resp.bits.data := Mux(pte.leaf(), Cat(pte.ppn, req_offset), SInt(-1, xLen).asUInt)
 
   io.busy := (state =/= s_idle)
   io.interrupt := Bool(false)