From 9bedde9a8a7317e601bf920a013ccea01b08f85e Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Tue, 17 Mar 2015 12:22:57 -0700 Subject: [PATCH] re-merge mem resp queues --- uncore/src/main/scala/memserdes.scala | 18 ++++-------------- 1 file changed, 4 insertions(+), 14 deletions(-) diff --git a/uncore/src/main/scala/memserdes.scala b/uncore/src/main/scala/memserdes.scala index 0a2b9c39..a5bea3a3 100644 --- a/uncore/src/main/scala/memserdes.scala +++ b/uncore/src/main/scala/memserdes.scala @@ -544,21 +544,11 @@ class MemPipeIOMemIOConverter(numRequests: Int, refillCycles: Int) extends Modul io.mem.req_data <> io.cpu.req_data // Have separate queues to allow for different mem implementations - val resp_dataq = Module((new HellaQueue(numEntries)) { new MemData }) - resp_dataq.io.enq.valid := io.mem.resp.valid - resp_dataq.io.enq.bits.data := io.mem.resp.bits.data + val resp_data_q = Module((new HellaQueue(numEntries)) { new MemResp }) + resp_data_q.io.enq <> io.mem.resp + io.cpu.resp <> resp_data_q.io.deq - val resp_tagq = Module((new HellaQueue(numEntries)) { new MemTag }) - resp_tagq.io.enq.valid := io.mem.resp.valid - resp_tagq.io.enq.bits.tag := io.mem.resp.bits.tag - - io.cpu.resp.valid := resp_dataq.io.deq.valid && resp_tagq.io.deq.valid - io.cpu.resp.bits.data := resp_dataq.io.deq.bits.data - io.cpu.resp.bits.tag := resp_tagq.io.deq.bits.tag - resp_dataq.io.deq.ready := io.cpu.resp.ready - resp_tagq.io.deq.ready := io.cpu.resp.ready - - inc := resp_dataq.io.deq.fire() + inc := resp_data_q.io.deq.fire() dec := io.mem.req_cmd.fire() && !io.mem.req_cmd.bits.rw }