Reg standardization

src/main/scala/RocketChip.scala

@@ -255,7 +255,7 @@ class Top extends Module {
   val io = new VLSITopIO(HTIF_WIDTH)
 
   val resetSigs = Vec.fill(uc.nTiles){Bool()}
-  val tileList = (0 until uc.nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))(rc)))
+  val tileList = (0 until uc.nTiles).map(r => Module(new Tile(_reset = resetSigs(r))(rc)))
   val uncore = Module(new Uncore(HTIF_WIDTH, tileList))
 
   var error_mode = Bool(false)

src/main/scala/fpga.scala

@@ -99,7 +99,7 @@ class FPGATop extends Module {
   val io = new FPGATopIO(htif_width)
 
   val resetSigs = Vec.fill(uc.nTiles){Bool()}
-  val tileList = (0 until uc.nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))(rc)))
+  val tileList = (0 until uc.nTiles).map(r => Module(new Tile(_reset = resetSigs(r))(rc)))
   val uncore = Module(new FPGAUncore(htif_width, tileList))
 
   io.debug.error_mode := Bool(false)

src/main/scala/network.scala

@@ -109,7 +109,7 @@ class ReferenceChipCrossbarNetwork(endpoints: Seq[CoherenceAgentRole])(implicit
   // Shims for converting between logical network IOs and physical network IOs
   //TODO: Could be less verbose if you could override subbundles after a <>
   def DefaultFromCrossbarShim[T <: Data](in: FBCIO[T]): FLNIO[T] = {
-    val out = Decoupled(new LogicalNetworkIO()(in.bits.payload.clone)).asDirectionless
+    val out = Decoupled(new LogicalNetworkIO()(in.bits.payload.clone))
     out.bits.header := in.bits.header
     out.bits.payload := in.bits.payload
     out.valid := in.valid
@@ -127,7 +127,7 @@ class ReferenceChipCrossbarNetwork(endpoints: Seq[CoherenceAgentRole])(implicit
     out
   }
   def DefaultToCrossbarShim[T <: Data](in: FLNIO[T]): FBCIO[T] = {
-    val out = Decoupled(new PhysicalNetworkIO()(in.bits.payload.clone)).asDirectionless
+    val out = Decoupled(new PhysicalNetworkIO()(in.bits.payload.clone))
     out.bits.header := in.bits.header
     out.bits.payload := in.bits.payload
     out.valid := in.valid