From 9b70ecf546ecc6a4f7f9e6e46e69a063c1370627 Mon Sep 17 00:00:00 2001
From: Henry Cook <hcook@eecs.berkeley.edu>
Date: Tue, 13 Aug 2013 17:53:19 -0700
Subject: [PATCH] Reg standardization

---
 chisel                          | 2 +-
 riscv-rocket                    | 2 +-
 src/main/scala/RocketChip.scala | 2 +-
 src/main/scala/fpga.scala       | 2 +-
 src/main/scala/network.scala    | 4 ++--
 uncore                          | 2 +-
 6 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/chisel b/chisel
index 97ac8785..58cb89a8 160000
--- a/chisel
+++ b/chisel
@@ -1 +1 @@
-Subproject commit 97ac878580bdd9bf9d4cf05d33d64689dfc6627a
+Subproject commit 58cb89a8831312a6a875372f9142fb444a593589
diff --git a/riscv-rocket b/riscv-rocket
index 2d3caa3e..744846b7 160000
--- a/riscv-rocket
+++ b/riscv-rocket
@@ -1 +1 @@
-Subproject commit 2d3caa3e269f238b1a8ccaa28f0c348dc12acf61
+Subproject commit 744846b72e7af011aca74fa5ded131552152af62
diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index d24f9881..e3fcbbac 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -255,7 +255,7 @@ class Top extends Module {
   val io = new VLSITopIO(HTIF_WIDTH)
 
   val resetSigs = Vec.fill(uc.nTiles){Bool()}
-  val tileList = (0 until uc.nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))(rc)))
+  val tileList = (0 until uc.nTiles).map(r => Module(new Tile(_reset = resetSigs(r))(rc)))
   val uncore = Module(new Uncore(HTIF_WIDTH, tileList))
 
   var error_mode = Bool(false)
diff --git a/src/main/scala/fpga.scala b/src/main/scala/fpga.scala
index 4a5a45ef..50590da3 100644
--- a/src/main/scala/fpga.scala
+++ b/src/main/scala/fpga.scala
@@ -99,7 +99,7 @@ class FPGATop extends Module {
   val io = new FPGATopIO(htif_width)
 
   val resetSigs = Vec.fill(uc.nTiles){Bool()}
-  val tileList = (0 until uc.nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r))(rc)))
+  val tileList = (0 until uc.nTiles).map(r => Module(new Tile(_reset = resetSigs(r))(rc)))
   val uncore = Module(new FPGAUncore(htif_width, tileList))
 
   io.debug.error_mode := Bool(false)
diff --git a/src/main/scala/network.scala b/src/main/scala/network.scala
index c60b727b..5b20491f 100644
--- a/src/main/scala/network.scala
+++ b/src/main/scala/network.scala
@@ -109,7 +109,7 @@ class ReferenceChipCrossbarNetwork(endpoints: Seq[CoherenceAgentRole])(implicit
   // Shims for converting between logical network IOs and physical network IOs
   //TODO: Could be less verbose if you could override subbundles after a <>
   def DefaultFromCrossbarShim[T <: Data](in: FBCIO[T]): FLNIO[T] = {
-    val out = Decoupled(new LogicalNetworkIO()(in.bits.payload.clone)).asDirectionless
+    val out = Decoupled(new LogicalNetworkIO()(in.bits.payload.clone))
     out.bits.header := in.bits.header
     out.bits.payload := in.bits.payload
     out.valid := in.valid
@@ -127,7 +127,7 @@ class ReferenceChipCrossbarNetwork(endpoints: Seq[CoherenceAgentRole])(implicit
     out
   }
   def DefaultToCrossbarShim[T <: Data](in: FLNIO[T]): FBCIO[T] = {
-    val out = Decoupled(new PhysicalNetworkIO()(in.bits.payload.clone)).asDirectionless
+    val out = Decoupled(new PhysicalNetworkIO()(in.bits.payload.clone))
     out.bits.header := in.bits.header
     out.bits.payload := in.bits.payload
     out.valid := in.valid
diff --git a/uncore b/uncore
index 295a4a5d..113ba96c 160000
--- a/uncore
+++ b/uncore
@@ -1 +1 @@
-Subproject commit 295a4a5d69987d58de5edea6fad4e750100cffa3
+Subproject commit 113ba96c49b7cff56ab93e55768838d59f8491d3