From 9b16d25861668509144ef1fc91c504b38f7c47a0 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Wed, 8 Nov 2017 16:46:25 -0800 Subject: [PATCH] Fix reporting of ITIM error addresses on slave-port accesses --- src/main/scala/rocket/ICache.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/rocket/ICache.scala b/src/main/scala/rocket/ICache.scala index 872ebc01..cc998775 100644 --- a/src/main/scala/rocket/ICache.scala +++ b/src/main/scala/rocket/ICache.scala @@ -255,7 +255,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer) val s1_clk_en = s1_valid || s1_slaveValid val s2_tag_hit = RegEnable(s1_tag_hit, s1_clk_en) val s2_hit_way = OHToUInt(s2_tag_hit) - val s2_scratchpad_word_addr = Cat(s2_hit_way, io.s2_vaddr(untagBits-1, log2Ceil(wordBits/8)), UInt(0, log2Ceil(wordBits/8))) + val s2_scratchpad_word_addr = Cat(s2_hit_way, Mux(s2_slaveValid, s1s3_slaveAddr, io.s2_vaddr)(untagBits-1, log2Ceil(wordBits/8)), UInt(0, log2Ceil(wordBits/8))) val s2_dout = RegEnable(s1_dout, s1_clk_en) val s2_way_mux = Mux1H(s2_tag_hit, s2_dout)