riscv/rocket-chip
1
0 Fork 0
Code Releases Activity

more itlb integration & cleanup

Browse Source
This commit is contained in:
Rimas Avizienis committed 2011-11-09 23:18:14 -08:00
1 parent c29d2821b4
commit 9aca403aa8
6 files changed
+13 -11
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

rocket/src/main/scala/ptw.scala
+2 -2
View File
@@ -83,8 +83,8 @@ class rocketPTW extends Component
io.itlb.resp_err := (state === s_error);
io.itlb.resp_perm := r_resp_perm;
io.itlb.resp_ppn :=
Mux(state === s_l1_fake, Cat(r_resp_ppn(PPN_BITS-1, PPN_BITS-7), r_req_vpn(VPN_BITS-8, 0)),
Mux(state === s_l2_fake, Cat(r_resp_ppn(PPN_BITS-1, PPN_BITS-17), r_req_vpn(VPN_BITS-18, 0)),
Mux(state === s_l1_fake, Cat(r_resp_ppn(PPN_BITS-1, PPN_BITS-7), r_req_vpn(VPN_BITS-11, 0)),
Mux(state === s_l2_fake, Cat(r_resp_ppn(PPN_BITS-1, PPN_BITS-17), r_req_vpn(VPN_BITS-21, 0)),
r_resp_ppn));
val resp_ptd = (io.dmem.resp_data(1,0) === Bits(1,2));