Add TLBuffers on the L1 backends and blind exit points (#513)

* [coreplex] add TLBuffers on the exit points from the Tile and Coreplex
* [config] WithBootROMFile

src/main/scala/coreplex/RocketTiles.scala

@@ -20,7 +20,7 @@ trait HasSynchronousRocketTiles extends CoreplexRISCVPlatform {
   }))}
 
   rocketTiles.foreach { r =>
-    r.masterNodes.foreach { l1tol2.node := _ }
+    r.masterNodes.foreach { l1tol2.node := TLBuffer()(_) }
     r.slaveNode.foreach { _ := cbus.node }
   }