diff --git a/src/main/scala/coreplex/Configs.scala b/src/main/scala/coreplex/Configs.scala
index 3a9c7801..558d1896 100644
--- a/src/main/scala/coreplex/Configs.scala
+++ b/src/main/scala/coreplex/Configs.scala
@@ -212,3 +212,7 @@ class WithoutFPU extends Config((site, here, up) => {
 class WithFPUWithoutDivSqrt extends Config((site, here, up) => {
   case FPUKey => Some(FPUConfig(divSqrt = false))
 })
+
+class WithBootROMFile(bootROMFile: String) extends Config((site, here, up) => {
+  case BootROMFile => bootROMFile
+})
diff --git a/src/main/scala/coreplex/CoreplexNetwork.scala b/src/main/scala/coreplex/CoreplexNetwork.scala
index fbfc707f..f14a8229 100644
--- a/src/main/scala/coreplex/CoreplexNetwork.scala
+++ b/src/main/scala/coreplex/CoreplexNetwork.scala
@@ -28,9 +28,9 @@ trait CoreplexNetwork extends HasCoreplexParameters {
   intBar.intnode := mmioInt
 
   cbus.node :=
+    TLBuffer()(
     TLAtomicAutomata(arithmetic = true)( // disable once TLB uses TL2 metadata
     TLWidthWidget(l1tol2_beatBytes)(
-    TLBuffer()(
     l1tol2.node)))
 
   mmio :=
diff --git a/src/main/scala/coreplex/RocketTiles.scala b/src/main/scala/coreplex/RocketTiles.scala
index 27181fa8..1286df67 100644
--- a/src/main/scala/coreplex/RocketTiles.scala
+++ b/src/main/scala/coreplex/RocketTiles.scala
@@ -20,7 +20,7 @@ trait HasSynchronousRocketTiles extends CoreplexRISCVPlatform {
   }))}
 
   rocketTiles.foreach { r =>
-    r.masterNodes.foreach { l1tol2.node := _ }
+    r.masterNodes.foreach { l1tol2.node := TLBuffer()(_) }
     r.slaveNode.foreach { _ := cbus.node }
   }
 
diff --git a/src/main/scala/rocketchip/BaseTop.scala b/src/main/scala/rocketchip/BaseTop.scala
index 442ffcf7..d89623ee 100644
--- a/src/main/scala/rocketchip/BaseTop.scala
+++ b/src/main/scala/rocketchip/BaseTop.scala
@@ -36,9 +36,10 @@ trait TopNetwork extends HasPeripheryParameters {
   val intBus = LazyModule(new IntXbar)
 
   peripheryBus.node :=
+    TLBuffer()(
     TLWidthWidget(socBusConfig.beatBytes)(
     TLAtomicAutomata(arithmetic = peripheryBusArithmetic)(
-    socBus.node))
+    socBus.node)))
 }
 
 trait TopNetworkBundle extends HasPeripheryParameters {
diff --git a/src/main/scala/rocketchip/Periphery.scala b/src/main/scala/rocketchip/Periphery.scala
index fa4db60c..64e95e6b 100644
--- a/src/main/scala/rocketchip/Periphery.scala
+++ b/src/main/scala/rocketchip/Periphery.scala
@@ -103,9 +103,9 @@ trait PeripheryMasterAXI4Mem {
   }
 
   val mem = mem_axi4.map { node =>
-    val foo = LazyModule(new TLToAXI4(config.idBits))
-    node := foo.node
-    foo.node
+    val converter = LazyModule(new TLToAXI4(config.idBits))
+    node := AXI4Buffer()(converter.node)
+    converter.node
   }
 }
 
@@ -140,10 +140,11 @@ trait PeripheryMasterAXI4MMIO {
     beatBytes = config.beatBytes))
 
   mmio_axi4 :=
+    AXI4Buffer()(
     // AXI4Fragmenter(lite=false, maxInFlight = 20)( // beef device up to support awlen = 0xff
     TLToAXI4(idBits = config.idBits)(      // use idBits = 0 for AXI4-Lite
     TLWidthWidget(socBusConfig.beatBytes)( // convert width before attaching to socBus
-    socBus.node))
+    socBus.node)))
 }
 
 trait PeripheryMasterAXI4MMIOBundle {
@@ -206,9 +207,10 @@ trait PeripheryMasterTLMMIO {
     beatBytes = config.beatBytes))
 
   mmio_tl :=
+    TLBuffer()(
     TLSourceShrinker(config.idBits)(
     TLWidthWidget(socBusConfig.beatBytes)(
-    socBus.node))
+    socBus.node)))
 }
 
 trait PeripheryMasterTLMMIOBundle {