Add TLBuffers on the L1 backends and blind exit points (#513)

* [coreplex] add TLBuffers on the exit points from the Tile and Coreplex
* [config] WithBootROMFile

src/main/scala/coreplex/Configs.scala

@@ -212,3 +212,7 @@ class WithoutFPU extends Config((site, here, up) => {
 class WithFPUWithoutDivSqrt extends Config((site, here, up) => {
   case FPUKey => Some(FPUConfig(divSqrt = false))
 })
+
+class WithBootROMFile(bootROMFile: String) extends Config((site, here, up) => {
+  case BootROMFile => bootROMFile
+})