Add TLBuffers on the L1 backends and blind exit points (#513)

* [coreplex] add TLBuffers on the exit points from the Tile and Coreplex
* [config] WithBootROMFile

src/main/scala/coreplex/Configs.scala

@@ -212,3 +212,7 @@ class WithoutFPU extends Config((site, here, up) => {
 class WithFPUWithoutDivSqrt extends Config((site, here, up) => {
   case FPUKey => Some(FPUConfig(divSqrt = false))
 })
+
+class WithBootROMFile(bootROMFile: String) extends Config((site, here, up) => {
+  case BootROMFile => bootROMFile
+})

src/main/scala/coreplex/CoreplexNetwork.scala

@@ -28,9 +28,9 @@ trait CoreplexNetwork extends HasCoreplexParameters {
   intBar.intnode := mmioInt
 
   cbus.node :=
+    TLBuffer()(
     TLAtomicAutomata(arithmetic = true)( // disable once TLB uses TL2 metadata
     TLWidthWidget(l1tol2_beatBytes)(
-    TLBuffer()(
     l1tol2.node)))
 
   mmio :=

src/main/scala/coreplex/RocketTiles.scala

@@ -20,7 +20,7 @@ trait HasSynchronousRocketTiles extends CoreplexRISCVPlatform {
   }))}
 
   rocketTiles.foreach { r =>
-    r.masterNodes.foreach { l1tol2.node := _ }
+    r.masterNodes.foreach { l1tol2.node := TLBuffer()(_) }
     r.slaveNode.foreach { _ := cbus.node }
   }