new paired meta/data IO type, and matching arbiter
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@ -8,6 +8,68 @@ import scala.collection.mutable.Stack
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implicit def toOption[A](a: A) = Option(a)
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implicit def toOption[A](a: A) = Option(a)
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class PairedDataIO[M <: Data, D <: Data]()(m: => M, d: => D) extends Bundle {
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val meta = (new FIFOIO()){ m }
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val data = (new FIFOIO()){ d }
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}
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class PairedArbiterIO[M <: Data, D <: Data](n: Int)(m: => M, d: => D) extends Bundle {
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val in = Vec(n) { new PairedDataIO()(m,d) }.flip
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val out = new PairedDataIO()(m,d)
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val meta_chosen = Bits(OUTPUT, log2Up(n))
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val data_chosen = Bits(OUTPUT, log2Up(n))
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}
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class PairedLockingRRArbiter[M <: Data, D <: Data](n: Int, count: Int, needsLock: Option[M => Bool] = None)(meta: => M, data: => D) {
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require(isPow2(count))
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val io = new PairedArbiterIO(n)(meta,data)
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val locked = if(count > 1) Reg(resetVal = Bool(false)) else Bool(false)
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val lockIdx = if(count > 1) Reg(resetVal = UFix(n-1)) else UFix(n-1)
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val grant = List.fill(n)(Bool())
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val meta_chosen = Bits(width = log2Up(n))
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val chosen_meta_has_data = io.out.meta.valid && needsLock.map(_(io.out.meta.bits)).getOrElse(Bool(true))
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(0 until n).map(i => io.in(i).meta.ready := grant(i) && io.out.meta.ready)
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(0 until n).map(i => io.in(i).data.ready := Mux(locked, lockIdx === UFix(i), grant(i) && chosen_meta_has_data) && io.out.data.ready)
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io.out.meta.valid := io.in(meta_chosen).meta.valid
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io.out.data.valid := Mux(locked, io.in(lockIdx).data.valid, io.in(meta_chosen).data.valid && chosen_meta_has_data)
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io.out.meta.bits := io.in(meta_chosen).meta.bits
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io.out.data.bits := Mux(locked, io.in(lockIdx).data.bits, io.in(meta_chosen).data.bits)
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io.meta_chosen := meta_chosen
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io.data_chosen := Mux(locked, lockIdx, meta_chosen)
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if(count > 1){
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val cnt = Reg(resetVal = UFix(0, width = log2Up(count)))
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val cnt_next = cnt + UFix(1)
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when(io.out.data.fire()){
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cnt := cnt_next
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when(cnt_next === UFix(0)) {
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locked := Bool(false)
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}
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}
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when(io.out.meta.fire()) {
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when(needsLock.map(_(io.out.meta.bits)).getOrElse(Bool(true))) {
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when(!locked) {
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locked := Bool(true)
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lockIdx := Vec(io.in.map{in => in.meta.fire()}){Bool()}.indexWhere{i: Bool => i}
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}
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}
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}
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}
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val last_grant = Reg(resetVal = Bits(0, log2Up(n)))
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val ctrl = ArbiterCtrl((0 until n).map(i => io.in(i).meta.valid && UFix(i) > last_grant) ++ io.in.map(_.meta.valid))
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(0 until n).map(i => grant(i) := ctrl(i) && UFix(i) > last_grant || ctrl(i + n))
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var choose = Bits(n-1)
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for (i <- n-2 to 0 by -1)
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choose = Mux(io.in(i).meta.valid, Bits(i), choose)
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for (i <- n-1 to 1 by -1)
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choose = Mux(io.in(i).meta.valid && UFix(i) > last_grant, Bits(i), choose)
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meta_chosen := choose
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when (io.out.meta.fire()) { last_grant := meta_chosen }
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}
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case class PhysicalNetworkConfiguration(nEndpoints: Int, idBits: Int)
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case class PhysicalNetworkConfiguration(nEndpoints: Int, idBits: Int)
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class PhysicalHeader(implicit conf: PhysicalNetworkConfiguration) extends Bundle {
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class PhysicalHeader(implicit conf: PhysicalNetworkConfiguration) extends Bundle {
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