From 9a3b2e7006c370b6c37bee57272a0d1788d50e5b Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Wed, 1 May 2013 16:48:01 -0700 Subject: [PATCH] new paired meta/data IO type, and matching arbiter --- uncore/src/package.scala | 62 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/uncore/src/package.scala b/uncore/src/package.scala index 7e1fc7a0..46c39d51 100644 --- a/uncore/src/package.scala +++ b/uncore/src/package.scala @@ -8,6 +8,68 @@ import scala.collection.mutable.Stack implicit def toOption[A](a: A) = Option(a) +class PairedDataIO[M <: Data, D <: Data]()(m: => M, d: => D) extends Bundle { + val meta = (new FIFOIO()){ m } + val data = (new FIFOIO()){ d } +} + +class PairedArbiterIO[M <: Data, D <: Data](n: Int)(m: => M, d: => D) extends Bundle { + val in = Vec(n) { new PairedDataIO()(m,d) }.flip + val out = new PairedDataIO()(m,d) + val meta_chosen = Bits(OUTPUT, log2Up(n)) + val data_chosen = Bits(OUTPUT, log2Up(n)) +} + +class PairedLockingRRArbiter[M <: Data, D <: Data](n: Int, count: Int, needsLock: Option[M => Bool] = None)(meta: => M, data: => D) { + require(isPow2(count)) + val io = new PairedArbiterIO(n)(meta,data) + val locked = if(count > 1) Reg(resetVal = Bool(false)) else Bool(false) + val lockIdx = if(count > 1) Reg(resetVal = UFix(n-1)) else UFix(n-1) + val grant = List.fill(n)(Bool()) + val meta_chosen = Bits(width = log2Up(n)) + + val chosen_meta_has_data = io.out.meta.valid && needsLock.map(_(io.out.meta.bits)).getOrElse(Bool(true)) + (0 until n).map(i => io.in(i).meta.ready := grant(i) && io.out.meta.ready) + (0 until n).map(i => io.in(i).data.ready := Mux(locked, lockIdx === UFix(i), grant(i) && chosen_meta_has_data) && io.out.data.ready) + io.out.meta.valid := io.in(meta_chosen).meta.valid + io.out.data.valid := Mux(locked, io.in(lockIdx).data.valid, io.in(meta_chosen).data.valid && chosen_meta_has_data) + io.out.meta.bits := io.in(meta_chosen).meta.bits + io.out.data.bits := Mux(locked, io.in(lockIdx).data.bits, io.in(meta_chosen).data.bits) + io.meta_chosen := meta_chosen + io.data_chosen := Mux(locked, lockIdx, meta_chosen) + + if(count > 1){ + val cnt = Reg(resetVal = UFix(0, width = log2Up(count))) + val cnt_next = cnt + UFix(1) + when(io.out.data.fire()){ + cnt := cnt_next + when(cnt_next === UFix(0)) { + locked := Bool(false) + } + } + when(io.out.meta.fire()) { + when(needsLock.map(_(io.out.meta.bits)).getOrElse(Bool(true))) { + when(!locked) { + locked := Bool(true) + lockIdx := Vec(io.in.map{in => in.meta.fire()}){Bool()}.indexWhere{i: Bool => i} + } + } + } + } + val last_grant = Reg(resetVal = Bits(0, log2Up(n))) + val ctrl = ArbiterCtrl((0 until n).map(i => io.in(i).meta.valid && UFix(i) > last_grant) ++ io.in.map(_.meta.valid)) + (0 until n).map(i => grant(i) := ctrl(i) && UFix(i) > last_grant || ctrl(i + n)) + + var choose = Bits(n-1) + for (i <- n-2 to 0 by -1) + choose = Mux(io.in(i).meta.valid, Bits(i), choose) + for (i <- n-1 to 1 by -1) + choose = Mux(io.in(i).meta.valid && UFix(i) > last_grant, Bits(i), choose) + meta_chosen := choose + + when (io.out.meta.fire()) { last_grant := meta_chosen } +} + case class PhysicalNetworkConfiguration(nEndpoints: Int, idBits: Int) class PhysicalHeader(implicit conf: PhysicalNetworkConfiguration) extends Bundle {