From 32592377c6e2c3e19a5aad5045caeb7e7f608540 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Thu, 8 Mar 2018 12:31:52 -0800 Subject: [PATCH 1/3] sbt: bump json4s-jackson to 3.5.3 --- build.sbt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/build.sbt b/build.sbt index f3cb18fd..f76a42a9 100644 --- a/build.sbt +++ b/build.sbt @@ -15,7 +15,7 @@ lazy val commonSettings = Seq( traceLevel := 15, scalacOptions ++= Seq("-deprecation","-unchecked"), libraryDependencies ++= Seq("org.scala-lang" % "scala-reflect" % scalaVersion.value), - libraryDependencies ++= Seq("org.json4s" %% "json4s-jackson" % "3.5.0"), + libraryDependencies ++= Seq("org.json4s" %% "json4s-jackson" % "3.5.3"), addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full) ) From d6e2c1a73fd41e0337dca147915256103483ff39 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Thu, 8 Mar 2018 12:36:51 -0800 Subject: [PATCH 2/3] more != wire deprecations --- src/main/scala/devices/debug/DebugTransport.scala | 2 +- src/main/scala/devices/tilelink/BusBypass.scala | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/devices/debug/DebugTransport.scala b/src/main/scala/devices/debug/DebugTransport.scala index e7e2363e..8a5fd888 100644 --- a/src/main/scala/devices/debug/DebugTransport.scala +++ b/src/main/scala/devices/debug/DebugTransport.scala @@ -172,7 +172,7 @@ class DebugTransportModuleJTAG(debugAddrBits: Int, c: JtagDTMConfig) // But there is actually no case in the current design where you SHOULD get an error, // as we haven't implemented Bus Masters or Serial Ports, which are the only cases errors // can occur. - nonzeroResp := stickyNonzeroRespReg | (io.dmi.resp.valid & (io.dmi.resp.bits.resp != UInt(0))) + nonzeroResp := stickyNonzeroRespReg | (io.dmi.resp.valid & (io.dmi.resp.bits.resp =/= UInt(0))) assert(!nonzeroResp, "There is no reason to get a non zero response in the current system."); assert(!stickyNonzeroRespReg, "There is no reason to have a sticky non zero response in the current system."); diff --git a/src/main/scala/devices/tilelink/BusBypass.scala b/src/main/scala/devices/tilelink/BusBypass.scala index 9668fb89..58884cfd 100644 --- a/src/main/scala/devices/tilelink/BusBypass.scala +++ b/src/main/scala/devices/tilelink/BusBypass.scala @@ -103,7 +103,7 @@ class TLBusBypassBar(implicit p: Parameters) extends LazyModule flight := next_flight when (next_flight === UInt(0)) { bypass := io.bypass } - val stall = (bypass != io.bypass) && a_first + val stall = (bypass =/= io.bypass) && a_first out0.a.valid := !stall && in.a.valid && bypass out1.a.valid := !stall && in.a.valid && !bypass From 1b93b27da4e23d2e0d5d4533cacec225b9961d39 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Thu, 8 Mar 2018 16:12:15 -0800 Subject: [PATCH 3/3] util: restore dontTouch annotation; Chisel's is broken on 0 element Aggregates --- src/main/scala/util/Misc.scala | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/main/scala/util/Misc.scala b/src/main/scala/util/Misc.scala index eabfa3af..fb34c3ef 100644 --- a/src/main/scala/util/Misc.scala +++ b/src/main/scala/util/Misc.scala @@ -4,7 +4,7 @@ package freechips.rocketchip.util import Chisel._ -import chisel3.experimental.{dontTouch, RawModule} +import chisel3.experimental.{ChiselAnnotation, RawModule} import freechips.rocketchip.config.Parameters import scala.math._ @@ -14,6 +14,13 @@ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait DontTouch { self: RawModule => + def dontTouch(data: Data): Unit = data match { + case agg: Aggregate => + agg.getElements.foreach(dontTouch) + case elt: Element => + annotate(ChiselAnnotation(elt, classOf[firrtl.Transform], "DONTtouch!")) + } + /** Marks every port as don't touch * * @note This method can only be called after the Module has been fully constructed