riscv/rocket-chip
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make Uncached generator vary the alloc bit

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This commit is contained in:
Howard Mao 2015-11-11 18:26:56 -08:00
parent 8a6b231b08
commit 9482d944ca
1 changed files with 3 additions and 2 deletions
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5
groundtest/src/main/scala/generator.scala
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@ -118,7 +118,8 @@ class UncachedTileLinkGenerator(id: Int)
addr_block = addr_block,
addr_beat = addr_beat,
data = beat_data,
wmask = Some(wmask))
wmask = Some(wmask),
alloc = req_cnt(0))
val get_acquire = Get(
client_xact_id = UInt(0),
@ -126,7 +127,7 @@ class UncachedTileLinkGenerator(id: Int)
addr_beat = addr_beat,
addr_byte = addr_byte,
operand_size = MT_D,
alloc = Bool(true))
alloc = req_cnt(0))
io.mem.acquire.valid := sending
io.mem.acquire.bits := Mux(state === s_put, put_acquire, get_acquire)