riscv/rocket-chip
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Use LinkedHashSet/Map for simpler determinism

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This commit is contained in:
Andrew Waterman
2014-03-15 17:31:48 -07:00
parent 53d62cb69d
commit 943d7ac80a
2 changed files with 6 additions and 15 deletions
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12
rocket/src/main/scala/ctrl.scala
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@ -406,19 +406,15 @@ class Control(implicit conf: RocketConfiguration) extends Module
(x.map(_._1).reduce(_||_), PriorityMux(x))
val fp_csrs = CSRs.fcsr :: CSRs.frm :: CSRs.fflags :: Nil
val legal_csrs = if (!conf.fpu.isEmpty) CSRs.all.toSet else CSRs.all.toSet -- fp_csrs
val legal_csrs = collection.mutable.LinkedHashSet(CSRs.all:_*)
if (conf.fpu.isEmpty)
legal_csrs --= fp_csrs
val id_csr_addr = io.dpath.inst(31,20)
val id_csr_en = id_csr != CSR.N
val id_csr_fp = Bool(!conf.fpu.isEmpty) && id_csr_en && DecodeLogic(id_csr_addr, fp_csrs, CSRs.all.toSet -- fp_csrs)
val id_csr_wen = id_raddr1 != UInt(0) || !Vec(CSR.S, CSR.C).contains(id_csr)
val legal_uint_csrs = new scala.collection.mutable.ArrayBuffer[Bits]
for (csr <- legal_csrs) {
legal_uint_csrs += UInt(csr)
}
val id_csr_invalid = id_csr_en && !Vec(legal_uint_csrs).contains(id_csr_addr)
val id_csr_invalid = id_csr_en && !Vec(legal_csrs.map(UInt(_))).contains(id_csr_addr)
val id_csr_privileged = id_csr_en &&
(id_csr_addr(11,10) === UInt(3) && id_csr_wen ||
id_csr_addr(11,10) === UInt(2) ||