riscv/rocket-chip
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Merge pull request #457 from ucb-bar/jtag-depth-1

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Jtag depth 1
This commit is contained in:
Wesley W. Terpstra 2016-11-25 18:41:39 -08:00 committed by GitHub
commit 9433da8458
2 changed files with 7 additions and 22 deletions
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25
src/main/scala/rocketchip/DebugTransport.scala
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@ -38,32 +38,25 @@ case object IncludeJtagDTM extends Field[Boolean]
* *
*/ */
class JtagDTMWithSync(depth: Int = 1, sync: Int = 3)(implicit val p: Parameters) class JtagDTMWithSync(implicit val p: Parameters) extends Module {
extends Module {
// io.DebugBusIO <-> Sync <-> DebugBusIO <-> UInt <-> DTM Black Box // io.DebugBusIO <-> Sync <-> DebugBusIO <-> UInt <-> DTM Black Box
val io = new Bundle { val io = new Bundle {
val jtag = new JTAGIO(true).flip val jtag = new JTAGIO(true).flip
val debug = new AsyncDebugBusIO val debug = new AsyncDebugBusIO
} }
val req_width = io.debug.req.mem(0).getWidth val req_width = io.debug.req.mem(0).getWidth
val resp_width = io.debug.resp.mem(0).getWidth val resp_width = io.debug.resp.mem(0).getWidth
val jtag_dtm = Module (new DebugTransportModuleJtag(req_width, resp_width)) val jtag_dtm = Module(new DebugTransportModuleJtag(req_width, resp_width))
jtag_dtm.io.jtag <> io.jtag jtag_dtm.io.jtag <> io.jtag
val dtm_req = Wire(new DecoupledIO(UInt(width = req_width)))
val dtm_resp = Wire(new DecoupledIO(UInt(width = resp_width)))
val io_debug_bus = Wire (new DebugBusIO) val io_debug_bus = Wire (new DebugBusIO)
io.debug <> ToAsyncDebugBus(io_debug_bus)
io.debug.req <> ToAsyncBundle(io_debug_bus.req) val dtm_req = jtag_dtm.io.dtm_req
io_debug_bus.resp <> FromAsyncBundle(io.debug.resp) val dtm_resp = jtag_dtm.io.dtm_resp
// Translate from straight 'bits' interface of the blackboxes // Translate from straight 'bits' interface of the blackboxes
// into the Resp/Req data structures. // into the Resp/Req data structures.
@ -74,20 +67,12 @@ class JtagDTMWithSync(depth: Int = 1, sync: Int = 3)(implicit val p: Parameters)
dtm_resp.valid := io_debug_bus.resp.valid dtm_resp.valid := io_debug_bus.resp.valid
dtm_resp.bits := io_debug_bus.resp.bits.asUInt dtm_resp.bits := io_debug_bus.resp.bits.asUInt
io_debug_bus.resp.ready := dtm_resp.ready io_debug_bus.resp.ready := dtm_resp.ready
dtm_req <> jtag_dtm.io.dtm_req
jtag_dtm.io.dtm_resp <> dtm_resp
} }
class DebugTransportModuleJtag(reqSize : Int, respSize : Int)(implicit val p: Parameters) extends BlackBox { class DebugTransportModuleJtag(reqSize : Int, respSize : Int)(implicit val p: Parameters) extends BlackBox {
val io = new Bundle { val io = new Bundle {
val jtag = new JTAGIO(true).flip() val jtag = new JTAGIO(true).flip()
val dtm_req = new DecoupledIO(UInt(width = reqSize)) val dtm_req = new DecoupledIO(UInt(width = reqSize))
val dtm_resp = new DecoupledIO(UInt(width = respSize)).flip() val dtm_resp = new DecoupledIO(UInt(width = respSize)).flip()
} }
} }

4
src/main/scala/util/AsyncBundle.scala
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@ -9,8 +9,8 @@ final class AsyncBundle[T <: Data](val depth: Int, gen: T) extends Bundle
{ {
require (isPow2(depth)) require (isPow2(depth))
val mem = Vec(depth, gen) val mem = Vec(depth, gen)
val ridx = UInt(width = log2Up(depth)+1).flip val ridx = UInt(width = log2Ceil(depth)+1).flip
val widx = UInt(width = log2Up(depth)+1) val widx = UInt(width = log2Ceil(depth)+1)
val ridx_valid = Bool().flip val ridx_valid = Bool().flip
val widx_valid = Bool() val widx_valid = Bool()
val source_reset_n = Bool() val source_reset_n = Bool()