From d755edffcc634215319a0c63ffeb03ae16a6e9be Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Fri, 25 Nov 2016 18:10:28 -0800 Subject: [PATCH 1/2] DebugTransport: use ToAsyncDebugBus for correct depth --- .../scala/rocketchip/DebugTransport.scala | 25 ++++--------------- 1 file changed, 5 insertions(+), 20 deletions(-) diff --git a/src/main/scala/rocketchip/DebugTransport.scala b/src/main/scala/rocketchip/DebugTransport.scala index 1d4949a3..596d6c52 100644 --- a/src/main/scala/rocketchip/DebugTransport.scala +++ b/src/main/scala/rocketchip/DebugTransport.scala @@ -38,32 +38,25 @@ case object IncludeJtagDTM extends Field[Boolean] * */ -class JtagDTMWithSync(depth: Int = 1, sync: Int = 3)(implicit val p: Parameters) - extends Module { - +class JtagDTMWithSync(implicit val p: Parameters) extends Module { // io.DebugBusIO <-> Sync <-> DebugBusIO <-> UInt <-> DTM Black Box val io = new Bundle { - val jtag = new JTAGIO(true).flip val debug = new AsyncDebugBusIO - } val req_width = io.debug.req.mem(0).getWidth val resp_width = io.debug.resp.mem(0).getWidth - val jtag_dtm = Module (new DebugTransportModuleJtag(req_width, resp_width)) - + val jtag_dtm = Module(new DebugTransportModuleJtag(req_width, resp_width)) jtag_dtm.io.jtag <> io.jtag - val dtm_req = Wire(new DecoupledIO(UInt(width = req_width))) - val dtm_resp = Wire(new DecoupledIO(UInt(width = resp_width))) - val io_debug_bus = Wire (new DebugBusIO) + io.debug <> ToAsyncDebugBus(io_debug_bus) - io.debug.req <> ToAsyncBundle(io_debug_bus.req) - io_debug_bus.resp <> FromAsyncBundle(io.debug.resp) + val dtm_req = jtag_dtm.io.dtm_req + val dtm_resp = jtag_dtm.io.dtm_resp // Translate from straight 'bits' interface of the blackboxes // into the Resp/Req data structures. @@ -74,20 +67,12 @@ class JtagDTMWithSync(depth: Int = 1, sync: Int = 3)(implicit val p: Parameters) dtm_resp.valid := io_debug_bus.resp.valid dtm_resp.bits := io_debug_bus.resp.bits.asUInt io_debug_bus.resp.ready := dtm_resp.ready - - dtm_req <> jtag_dtm.io.dtm_req - jtag_dtm.io.dtm_resp <> dtm_resp } class DebugTransportModuleJtag(reqSize : Int, respSize : Int)(implicit val p: Parameters) extends BlackBox { - val io = new Bundle { val jtag = new JTAGIO(true).flip() - val dtm_req = new DecoupledIO(UInt(width = reqSize)) - val dtm_resp = new DecoupledIO(UInt(width = respSize)).flip() - } - } From 233280e7d2b25c7d287d8904ca7fa48033d246ee Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Fri, 25 Nov 2016 18:11:01 -0800 Subject: [PATCH 2/2] AsyncBundle: save a wasted bit when depth=1 --- src/main/scala/util/AsyncBundle.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/util/AsyncBundle.scala b/src/main/scala/util/AsyncBundle.scala index fb178666..81057779 100644 --- a/src/main/scala/util/AsyncBundle.scala +++ b/src/main/scala/util/AsyncBundle.scala @@ -9,8 +9,8 @@ final class AsyncBundle[T <: Data](val depth: Int, gen: T) extends Bundle { require (isPow2(depth)) val mem = Vec(depth, gen) - val ridx = UInt(width = log2Up(depth)+1).flip - val widx = UInt(width = log2Up(depth)+1) + val ridx = UInt(width = log2Ceil(depth)+1).flip + val widx = UInt(width = log2Ceil(depth)+1) val ridx_valid = Bool().flip val widx_valid = Bool() val source_reset_n = Bool()