riscv/rocket-chip
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Avoid type-unsafe assignments

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This commit is contained in:
Andrew Waterman 2015-08-27 09:57:36 -07:00
parent 05d311c517
commit 94287fed90
1 changed files with 4 additions and 4 deletions
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8
uncore/src/main/scala/cache.scala
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@ -364,7 +364,7 @@ class TSHRFile extends L2HellaCacheModule with HasCoherenceAgentWiringHelpers {
doInternalInputRouting(wb.io.wb.resp, trackerList.map(_.io.wb.resp)) doInternalInputRouting(wb.io.wb.resp, trackerList.map(_.io.wb.resp))
// Propagate incoherence flags // Propagate incoherence flags
(trackerList.map(_.io.incoherent) :+ wb.io.incoherent) foreach { _ := io.incoherent.toBits } (trackerList.map(_.io.incoherent) :+ wb.io.incoherent) foreach { _ := io.incoherent }
// Handle acquire transaction initiation // Handle acquire transaction initiation
val trackerAcquireIOs = trackerList.map(_.io.inner.acquire) val trackerAcquireIOs = trackerList.map(_.io.inner.acquire)
@ -525,7 +525,7 @@ class L2VoluntaryReleaseTracker(trackerId: Int) extends L2XactTracker {
io.data.write.bits.way_en := xact_way_en io.data.write.bits.way_en := xact_way_en
io.data.write.bits.addr_idx := xact.addr_block(idxMSB,idxLSB) io.data.write.bits.addr_idx := xact.addr_block(idxMSB,idxLSB)
io.data.write.bits.addr_beat := curr_write_beat io.data.write.bits.addr_beat := curr_write_beat
io.data.write.bits.wmask := SInt(-1) io.data.write.bits.wmask := ~UInt(0, io.data.write.bits.wmask.getWidth)
io.data.write.bits.data := data_buffer(curr_write_beat) io.data.write.bits.data := data_buffer(curr_write_beat)
// Send an acknowledgement // Send an acknowledgement
@ -663,7 +663,7 @@ class L2AcquireTracker(trackerId: Int) extends L2XactTracker {
wmask & Mux(xact.isBuiltInType(Acquire.putAtomicType), wmask & Mux(xact.isBuiltInType(Acquire.putAtomicType),
amoalu.io.out << xact.amo_shift_bits(), amoalu.io.out << xact.amo_shift_bits(),
new_data) new_data)
wmask_buffer(beat) := SInt(-1) wmask_buffer(beat) := ~UInt(0, wmask_buffer.head.getWidth)
when(xact.is(Acquire.putAtomicType) && xact.addr_beat === beat) { amo_result := old_data } when(xact.is(Acquire.putAtomicType) && xact.addr_beat === beat) { amo_result := old_data }
} }
def mergeDataInternal[T <: HasL2Data with HasL2BeatAddr](in: ValidIO[T]) { def mergeDataInternal[T <: HasL2Data with HasL2BeatAddr](in: ValidIO[T]) {
@ -1057,7 +1057,7 @@ class L2WritebackUnit(trackerId: Int) extends L2XactTracker {
val coh = io.wb.req.bits.coh val coh = io.wb.req.bits.coh
val needs_inner_probes = coh.inner.requiresProbesOnVoluntaryWriteback() val needs_inner_probes = coh.inner.requiresProbesOnVoluntaryWriteback()
when(needs_inner_probes) { pending_iprbs := coh.inner.full() & ~io.incoherent.toBits } when(needs_inner_probes) { pending_iprbs := coh.inner.full() & ~io.incoherent.toBits }
pending_reads := SInt(-1, width = innerDataBeats) pending_reads := ~UInt(0, width = innerDataBeats)
pending_resps := UInt(0) pending_resps := UInt(0)
pending_orel_data := UInt(0) pending_orel_data := UInt(0)
state := Mux(needs_inner_probes, s_inner_probe, s_busy) state := Mux(needs_inner_probes, s_inner_probe, s_busy)