riscv/rocket-chip
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[groundtest] testramaddr constant in package

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This commit is contained in:
Henry Cook
2016-11-16 18:42:56 -08:00
parent e1992d7c55
commit 92e233d596
3 changed files with 5 additions and 2 deletions
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src/main/scala/groundtest/Coreplex.scala
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@@ -22,7 +22,7 @@ class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex
l1tol2.node := lm.uncachedOut
}
val cbusRAM = LazyModule(new TLRAM(AddressSet(0x10000, 0xffff), false, cbus_beatBytes))
val cbusRAM = LazyModule(new TLRAM(AddressSet(testRamAddr, 0xffff), false, cbus_beatBytes))
cbusRAM.node := TLFragmenter(cbus_beatBytes, cbus_lineBytes)(cbus.node)
override lazy val module = new GroundTestCoreplexModule(this, () => new GroundTestCoreplexBundle(this))