diff --git a/src/main/scala/groundtest/Coreplex.scala b/src/main/scala/groundtest/Coreplex.scala
index 9aac2672..f1358cbc 100644
--- a/src/main/scala/groundtest/Coreplex.scala
+++ b/src/main/scala/groundtest/Coreplex.scala
@@ -22,7 +22,7 @@ class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex
     l1tol2.node := lm.uncachedOut
   }
 
-  val cbusRAM = LazyModule(new TLRAM(AddressSet(0x10000, 0xffff), false, cbus_beatBytes))
+  val cbusRAM = LazyModule(new TLRAM(AddressSet(testRamAddr, 0xffff), false, cbus_beatBytes))
   cbusRAM.node := TLFragmenter(cbus_beatBytes, cbus_lineBytes)(cbus.node)
 
   override lazy val module = new GroundTestCoreplexModule(this, () => new GroundTestCoreplexBundle(this))
diff --git a/src/main/scala/groundtest/Package.scala b/src/main/scala/groundtest/Package.scala
new file mode 100644
index 00000000..e91d9fd1
--- /dev/null
+++ b/src/main/scala/groundtest/Package.scala
@@ -0,0 +1,3 @@
+package object groundtest {
+  val testRamAddr = 0x10000
+}
diff --git a/src/main/scala/groundtest/Regression.scala b/src/main/scala/groundtest/Regression.scala
index 6699f2e1..81376990 100644
--- a/src/main/scala/groundtest/Regression.scala
+++ b/src/main/scala/groundtest/Regression.scala
@@ -72,7 +72,7 @@ class IOGetAfterPutBlockRegression(implicit p: Parameters) extends Regression()(
   io.mem.grant.ready := Bool(true)
 
   io.cache.req.valid := !get_sent && started
-  io.cache.req.bits.addr := UInt(addrMap("TL2:bootrom").start)
+  io.cache.req.bits.addr := UInt(testRamAddr)
   io.cache.req.bits.typ := MT_WU
   io.cache.req.bits.cmd := M_XRD
   io.cache.req.bits.tag := UInt(0)